Fujitsu Corporation

Mitsui Minings & Melting Co., Ltd.

Tokyo Institute of Technology

Yoshihiro Arimoto

Sadahiro Kishii

Ko Nakamura

Hiroshi Horie

Akiyoshi Hatada

Fumitoshi Sugimoto

Rintaro Suzuki

Atsushi Fukuroda

Tatsuya Ohori

Isamu Hanyu

Masao Kondo

Kazuhiro Takahashi

Kenji Maruyama

Kenzo Hanawa

Shigeo Kodama

Masaki Kurasawa

Tetsuro Tamura

Hiroshi Ishihara

Hideki Yamawaki

Masaomi Yamaguchi

Takafumi Kimura

Masaru Ihara

Naruo Ueda

Hiromasa Hoko

Yasuo Nara

Koji Aizawa

Yoshiaki Tabuchi

Satoshi Hasegawa

Maki Murazumi

A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substratehaving a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film' containing Pb and having a plane (111)in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and partof a circuit of a semiconductor device, to thereby fabricate the single crystalline substratehaving said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrateto another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together. The capacitor in the semiconductor device thus obtained includes a ferroelectric thin film having a large amount of polarizing charge. The semiconductor device can be used as a highly reliable nonvolatile memory.

Method of producing semiconductor device

A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.

Ferroelectric memory, multivalent data recording method and multivalent data reading method

A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

Slurry containing manganese oxide and a fabrication process of a

A method of fabricating a semiconductor device includes a step of polishing a surface of a substrate by a chemical mechanical polishing process conducted on a polishing cloth by a slurry. The polishing is conducted so that projections having a height of about 30 .mu.m or less are formed on the polishing cloth with an interval of about 55 .mu.m or less as a result of the polishing.

Polishing cloth for use in a CMP process and a surface treatment thereof

A polishing apparatus comprises a first surface plate for supporting a polishing object, a driving mechanism for rotating the first surface plate, a second surface plate arranged so as to oppose to the first surface plate, an abrasive cloth stuck to the second surface plate, a vibration detector attached to the first surface plate or the second surface plate for detecting vibration in polishing, a controlling portion for controlling polishing operation of the first surface plate and the second surface plate, and signal analyzing unit for analyzing vibration intensity detected by the a vibration detector through frequency analysis, integrating the vibration intensity relative to time, and transmitting a polishing stop signal to stop polishing operation of the first surface plate and the second surface plate to the controlling portion when variation in a resultant integral value relative to time is less than a first reference value or when the resultant integral value is less than a second reference value.

Polishing apparatus and polishing method

Slurry containing manganese oxide

Fabrication process of a semiconductor device using a slurry containing

For providing a method for polishing in which it is possible to polish a substance uniformly over a whole surface of a wafer without observing the polished surface of the wafer halfway through polishing, a wafer with current detective patterns formed of conductors directly contacted with a semiconductor substrate, and an insulating film covering the current detective patterns is held by a wafer holder with conductivity, and the insulating film is polished by a polisher in which a supporting plate with conductivity is exposed in openings through a polishing cloth while supplying a polishing slurry containing ions.

Apparatus and method for uniformly polishing a wafer

In a semiconductor device, first and second substrates are supported with respective first major surfaces in opposing, parallel and spaced relationship. A conductor layer of low resistivity material is provided on a selected one of the opposing and spaced major surfaces, in intimate contact and spaced from the opposed major surface of the other substrate. An active device is formed in the first substrate with a region electrically connected to the conductor layer. A contact region is exposed at the second major surface of the first substrate and extends through the first substrate and into electrical contact with the conductor layer.

SOI device having a buried layer of reduced resistivity

An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.

A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.

Composite semiconductor substrate having a single crystal substrate and

A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.

Composite semiconductor substrate and a fabrication process thereof

Method of and apparatus for manufacturing a semiconductor substrate

Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.

Process for the production of semiconductor devices utilizing multi-step

Growing community of inventors

Kawasaki, Japan

Yoshihiro Arimoto