Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Yoshihiro Akutsu

Ryota Katsumata

Masaru Kito

Masaru Kidoh

Yoshiaki Fukuzumi

Mitsuru Sato

Megumi Ishiduki

Tadashi Iguchi

Hiroshi Shinohara

Tsuneo Uenaka

Satoshi Konagai

Atsushi Konno

This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Non-volatile semiconductor memory device and manufacturing method thereof

According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.

Three dimensional vertical channel semiconductor memory device

In general, according to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first sub-conductive layer, a first insulating film. One portion of the first conductive layer overlaps at least one portion of the first sub-conductive layer in the first direction. One other portion of the first conductive layer overlaps at least one portion of the second conductive layer in the first direction. One portion of the first insulating film overlaps at least one portion of the second conductive layer in the second direction. The One portion of the first insulating film overlaps one portion of the first sub-conductive layer in the second direction. The second conductive layer overlap one other portion of the first insulating film in a direction intersecting the second direction.

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and a first interconnect. When an imaginary first straight line extending in a second direction crossing a first direction is set, the plurality of columnar portions are divided into first sets of n (n is an integer number not less than 3 and not more than 32) columnar portions with center axes alternately disposed on both sides of the first straight line along the second direction and second sets of n columnar portions having position relationships of inversion of the first sets with respect to the first straight line, and the first sets and the second sets are alternately arranged.

Semiconductor memory device

According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other.

Non-volatile memory device, method for fabricating pattern on wafer and method for manufacturing non-volatile memory device using same

According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer.

Nonvolatile semiconductor memory device and method for manufacturing same

According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

Growing community of inventors

Yokkaichi, Japan

Yoshihiro Akutsu