Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Yoshihiko Toyoda

Takeshi Mori

Tetsuo Fukada

Makiko Hasegawa

Kazuyuki Sugahara

Takao Sakamoto

Naoki Nakagawa

Yoshiyuki Kitazawa

Takeharu Kuroiwa

Takanori Tanaka

Satoshi Yamakawa

Nobuyuki Tomita

Zempei Kawazu

Kenichi Hamano

Takumi Nakahata

Yoichiro Mitani

Kiyoshi Hayashi

Akihito Ono

Naoyuki Kawabata

Junji Ochi

Taro Yoshino

A method for manufacturing a SiC epitaxial wafer includes: a first step of, by supplying a Si supply gas and a C supply gas, performing a first epitaxial growth on a SiC bulk substrate with a 4H&#x2014;SiC(0001) having an off-angle of less than 5&#xb0; as a main surface at a first temperature of 1480&#xb0; C. or higher and 1530&#xb0; C. or lower; a second step of stopping the supply of the Si supply gas and the C supply gas and increasing a temperature of the SiC bulk substrate from the first temperature to a second temperature; and a third step of, by supplying the Si supply gas and the C supply gas, performing a second epitaxial growth on the SiC bulk substrate having the temperature increased in the second step at the second temperature.

Method for manufacturing SiC epitaxial wafer

A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.

Semiconductor device with multiple impurity regions and image display apparatus

A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

Fabrication method of a semiconductor device

A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 &#x3bc;m) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 &#x3bc;m) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

Semiconductor device

Photosensitive insulating films are laminated on lower-layer interconnection layers and a connection hole is formed in the photosensitive insulating film, and a interconnection groove is formed in the photosensitive insulating film. The upper-layer interconnection layers fill the connection hole and the groove. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method producing a multi-layer interconnection structure, in which the connection hole and the groove are formed in a simple process, yield is improved, and the number of process steps and cost are reduced.

Semiconductor device and manufacturing method thereof

Chip element formation areas and scribe line areas dividing the chip formation areas are formed on a wafer. On each scribe line area, an interconnection surrounds each chip formation area, and extends to near an edge of a wafer. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method which can reduce a difference in the depositing rate of plating between the center and the periphery of the wafer.

The electroplating apparatus includes a substrate disposed above an insoluble anode and a filter disposed between the insoluble anode and the substrate for removing oxygen generated at the insoluble anode. This plating apparatus using an insoluble anode allows easy placement and removal of the substrate and prevents poor deposition and poor filling caused by accumulation, on the substrate, of oxygen generated at the insoluble anode.

Electroplating apparatus

A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.

Semiconductor device and method of fabricating the same

A semiconductor device capable of preventing diffusion of a particle of copper or the like which forms a conductive layer is provided without any increase in the number of manufacturing the steps. Further, a semiconductor device preventing diffusion of a particle forming a conductive layer into an insulating layer even when a width of the conductive layer is increased is provided. The semiconductor device includes: an insulating layer a barrier layer a conductive layer a barrier layer having an opening an insulating layer having a through hole exposing a surface of conductive layer and a part of a surface of barrier layer a barrier layer formed on a surface of said through hole and insulating layer which is in contact with an upper surface of barrier layer and a conductive layer filling opening and through hole

Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.

Method of forming thin copper film and semiconductor device with thin copper film

A highly reliable semiconductor device having a contact hole with a sufficient area can be obtained. An interlevel insulating film is formed on a conductive region having a first width. A through hole which exposes the conductive region is formed at the interlevel insulating film. A coating film is formed on the interlevel insulating film. In the coating film, an opening having a second width larger than the first width is formed in a region located on the through hole. An interconnect line is formed in a region located on the opening. A conductor film for electrically connecting the conductive region and the interconnect line is generated within the through hole.

Semiconductor device having interconnect layer and method of manufacturing therefor

A method of preparing a multilevel embedded wiring system for an IC comprising a first wiring formation step, a first connecting portion formation step, and a second wiring formation step, wherein the first wiring formation step comprises forming a first trench for a first embedded wiring in a first insulating layer disposed on a substrate and embedding in the first trench, in turn, a first conductive layer and a first conductive capping layer; the first connecting portion formation step comprises forming a second insulating layer on the first insulating layer and the first conductive capping layer, forming a via-hole in a part of the second insulating layer at the first conductive capping layer, and embedding a conductive connecting portion in the via-hole and connected to the first conductive layer; and the second formation step comprises forming a third insulating layer on the second insulating layer and the conductive connecting portion, forming a second trench for a second wiring in the third insulating layer at the conductive connecting portion, and embedding a second conductive layer in the second trench and connected to the conductive connecting portion.

Method of making embedded wiring system

A Cu interconnection layer is formed in a trench provided in an insulating layer with a base layer interposed therebetween, an adhesion layer is formed on the Cu interconnection layer and a cap layer is formed on the adhesion layer to restrict exfoliation of the cap layer formed on the Cu interconnection layer buried in the trench formed in the insulating layer.

Semiconductor device having interconnection and adhesion layers

In a CVD apparatus for Cu formation using as a raw material, a mixture of a solvent and a liquid raw material including Cu(HFA) and adducted molecules or a solid raw material including Cu(HFA) and adducted molecules, a fluorinated organic polymer contained, a fluorinated metal, an insulator or a Ti compound is provided on a surface of a member at a portion where the raw material exists.

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Hyogo, Japan

Yoshihiko Toyoda