Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Yoshihiko Sumimoto

Tomonori Fujimoto

Kiyoto Oota

Masataka Kondo

Kiyoto Ohta

Upon conduct of a test on a semiconductor memory in a merged LSI or the like, data signals from a small data bus width are simultaneously written to a plurality of memory cells of a memory core. Then, a coincidence detection circuit makes a comparison between data read from the plurality of memory cells in expectation of a coincidence thereof. When the coincidence detection circuit detects the coincidence of the data, a data compression circuit compresses the compared data, and then outputs the compressed data. On the other hand, when the coincidence detection circuit detects an anticoincidence of the data, the data compression circuit converts the different data into fixed data, and then outputs the converted data.

Semiconductor memory with a circuit for testing the same

By simplifying the shape of memory cell diffused mask patterns, the patterns are formed stably and the yield of a semiconductor memory device is improved. Adjacent 2-bit memory cell transistors are formed with one diffused mask pattern, the diffused mask patterns are arranged on a memory cell array, and metal lines are used as source common lines for the memory cells formed at the diffused mask patterns. In this way, that is, by using 2-bit rectangular diffused mask patterns as the memory cell diffused mask patterns and using the metal lines as the source common lines instead of diffused layers, the shape of the memory cell diffused mask patterns is simplified. And furthermore, the continuity of the memory cell diffused mask patterns used as actual memory cells is kept, accuracy in forming the actual memory cell diffused mask patterns is improved, and the yield of the semiconductor memory device is improved.

Semiconductor memory device and method for generating ROM data pattern

A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.

Semiconductor circuit having a detection circuit for controlling a power boosting circuit

Semiconductor integrated circuit

An LSI on which a DRAM is mounted together with a logic part, which does not require the level shifter control signal so as to simplify the circuit configuration and reduces power consumption. This LSI includes a level shifter and an interface circuit . The level shifter converts the operation voltage level of the DRAM control signal and input data output from the logic part operating with a low voltage power supply, and outputs the DRAM control signal to a DRAM . The interface circuit controls the input data output from the level shifter and the output data output from the DRAM by an interface control signal supplied from the DRAM , outputs the input data into the DRAM and outputs the output data to the external data output terminal and the logic part.

Growing community of inventors

Osaka, Japan

Yoshihiko Sumimoto