Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Yonezawa Electronics Co., Ltd

Renesas Northern Japan Semiconductor, Inc.

Other

Renesas Semiconductor Package & Test Solutions Co., Ltd.

Yoshihiko Shimanuki

Koji Tsuchiya

Yoshihiro Suzuki

Masayuki Suzuki

Hisashi Hasunuma

Hiromichi Suzuki

Yoshinori Miyaki

Fujio Ito

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

Semiconductor device

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

Semiconductor device and manufacturing method thereof

A semiconductor device manufacturing method which improves working efficiency. The method includes the step of transporting by air a package as a sealed moisture-proof bag which contains a case housing a semiconductor wafer laminate, in which the semiconductor wafer laminate has a plurality of semiconductor wafers stacked with a protective sheet interposed between semiconductor wafers. In order to facilitate separation of the protective sheet from the semiconductor wafers after unpacking the package, the protective sheet has a plurality of convex parts, a plurality of concave parts, and a flat part between a convex part and a concave part. A hole penetrating the protective sheet is made in each convex part and the center of the hole is located off the apex of the convex part.

Semiconductor device manufacturing method

The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

There are constituted by a tab on which a semiconductor chip is mounted, a sealing portion formed by resin-sealing the semiconductor chip, a plurality of leads each having a mounted surface exposed to a peripheral portion of a rear surface of the sealing portion and a sealing-portion forming surface disposed on an opposite side thereto, and a wire for connecting a pad of the semiconductor chip and a lead, wherein the length between inner ends of the sealing-portion forming surfaces of the leads disposed so as to oppose to each other is formed to be larger than the length between inner ends of the mounted surfaces. Thereby, a chip mounting region surrounded by the inner end of the sealing-portion forming surface of each lead can be expanded and the size of the mountable chip is increased.

There are constituted by a tab () on which a semiconductor chip () is mounted, a sealing portion () formed by resin-sealing the semiconductor chip (), a plurality of leads () each having a mounted surface () exposed to a peripheral portion of a rear surface () of the sealing portion () and a sealing-portion forming surface () disposed on an opposite side thereto, and a wire () for connecting a pad () of the semiconductor chip () and a lead (), wherein the length (M) between inner ends () of the sealing-portion forming surfaces () of the leads () disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends () of the mounted surfaces (). Thereby, a chip mounting region surrounded by the inner end () of the sealing-portion forming surface () of each lead () can be expanded and the size of the mountable chip is increased.

A semiconductor device is disclosed which includes a tab () for use in supporting a semiconductor chip (), a seal section () as formed by sealing the semiconductor chip () with a resin material, more than one tab suspension lead () for support of the tab (), a plurality of electrical leads () which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section () and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove () and outer groove () in a wire bonding surface () as disposed within the seal section () of said to-be-connected portion, and wires () for electrical connection between the leads () and pads () of the semiconductor chip (), wherein said thickness reduced portion of the leads () is covered by or coated with a sealing resin material while causing the wires () to be contacted with said to-be-connected portion at specified part lying midway between the outer groove () and inner groove () to thereby permit said thickness reduced portion of leads () and the outer groove () plus the inner groove () to prevent occurrence of any accidental lead drop-down detachment.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

The method of manufacture includes preparing a wiring board which has a front surface and an opposing rear surface, a plurality of conductive portions which are formed on the front and rear surfaces of the core material thereof, respectively, forming a first resist film and a second resist film on the front surface and rear surface of the core material, respectively, such that the conductive portions are exposed therefrom; mounting the semiconductor chip to the main surface side of the wiring board via adhesive material; electrically connecting the pads provided on the semiconductor chip, with the first conductive portions of the wiring board via bonding wires, respectively; and sealing the semiconductor chip and the bonding wires.

Growing community of inventors

Nanyo, Japan

Yoshihiko Shimanuki