Denso Corporation

Nippon Soken, Inc.

Yoshihiko Ozeki

Norihito Tokura

Yukio Tsuzuki

Tetsuo Fujii

Shigeki Takahashi

Kenji Kouno

Yoshifumi Okabe

Kazuyoshi Nagase

Kensaku Yamamoto

Koji Kondo

Hiroyuki Mori

Hisanori Yokura

Youichirou Suzuki

Naoto Okabe

Noboru Maeda

Takashi Nakano

Norio Sanma

Takeshi Fukazawa

Naohito Kato

Yutaka Tomatsu

Haruo Kawakita

A semiconductor device includes a semiconductor substrate that includes a plurality of section having different thicknesses. The sections include a first section having a first thickness and a second section having a second thickness, the second section is the thinnest section among all the sections, and the first thickness is greater than the second thickness. A plurality of isolation trenches penetrates the semiconductor substrate for defining a plurality of element-forming regions in the first section and the second section. A plurality of elements is located at respective ones of the plurality of element-forming regions. The elements include a double-sided electrode element that includes a pair of electrodes separately disposed on the first surface and the second surface, and the double-sided electrode element is located in the second section.

Semiconductor device having a plurality of elements on one semiconductor substrate and method of manufacturing the same

A receiving device includes a receiving circuit and an impedance control circuit. The receiving circuit receives a signal transmitted through a communication line. The impedance control circuit is coupled with the receiving circuit and has a detecting part. The detecting part detects a physical value of the signal and the physical value includes at least one of a voltage, an electric current, and an electric power. The impedance control circuit changes an input impedance based on the detected value so that a ringing of the signal is reduced.

Receiving device including impedance control circuit and semiconductor device including impedance control circuit

A signal transmission circuit is capable of reducing distortion that occurs during signal transmission. A digital output signal is transmitted from a terminal to a signal line via an output buffer circuit and an output impedance unit. The terminal is connected to an impedance variation unit via an impedance control unit. The impedance variation unit designates an impedance for terminating the signal line when the output data is changed from a high level H to a low level. A reflection occurring on the signal line can be prevented and a waveform distortion can be suppressed.

Signal transmission circuit

A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

Semiconductor device having IGBT and diode

A semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner even when the active and passive elements include double sided electrode elements. When the semiconductor substrate is divided into plural field areas, an insulation separation trench that penetrates the semiconductor substrate surrounds each of the field areas, and each of the either of the plural active elements or the plural passive elements. Further, each of the plural elements has a pair of power electrodes for power supply respectively disposed on each of both sides of the semiconductor substrate to serve as the double sided electrode elements.

Semiconductor device and method for manufacturing same

A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.

Semiconductor device having IGBT element

A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 &#x3bc;m.

Trench gate type semiconductor device

A trench gate type IGBT includes: a first semiconductor layer; a second semiconductor on the first semiconductor layer; a third semiconductor on the second semiconductor layer; trenches for separating the third semiconductor layer into first regions and second regions; a gate insulation film on an inner wall of each trench; a gate electrode on the gate insulation film; a fourth semiconductor layer in a surface portion of each first region and contacting each trench; a first electrode connecting to the first region and the fourth semiconductor layer; and a second electrode connecting to the first semiconductor layer. The first regions and the second regions are alternately arranged. Two second regions are continuously connected together to be integrated into one body.

Trench gate type insulated gate bipolar transistor

A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.

In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.

Semiconductor device with peripheral portion for withstanding surge voltage

A vertical power MOSFET, which can improve a surge withstand voltage and a surge withstand voltage against a surge voltage from an inductance load L. The vertical power MOSFET has a plurality of unit cells. The unit cell is formed from a MOSFET that uses a p-type base layer at a sidewall of a rectangular U-groove as a channel portion. Each of the p-type base layer of each unit cell is connected each others Accordingly, it can restrain an impurity concentration of a corner portion (a portion positioned at a corner) of the rectangular p-type base layer from being decreased. Therefore, it can reduce the difference in distance from the end portion of the p-type base layer to the end portion of the depletion layer. As a result, it can improve the surge withstand voltage when a surge voltage is input from an inductance load L.

Vertical type MOSFET

A method of manufacturing of a semiconductor device having a thermal oxidation process for selectively forming an oxide film by a thermal oxidation, which can reduce the generation of lattice defects in the semiconductor device during the thermal oxidation process. A groove portion LOCOS oxide film is formed in a groove portion of a semiconductor substrate by first and second wet oxidation steps. At the first wet oxidation step, a thin oxide film is formed on an exposed surface of an epitaxial layer by performing a wet oxidation through an opening portion made of silicon nitride under an oxidation temperature of approximately 875&deg; C. At the second wet oxidation step, the oxidation temperature is risen to approximately 1050&deg; C. to advance the oxidation of the epitaxial layer to finally form the groove portion LOCOS oxide film having a thickness of approximately 950 nm. Lattice defects due to the dislocation is reduced by largely releasing the thermal stress generated at the semiconductor substrate portion corresponding to the edges of the groove portion LOCOS oxide film. Therefore, it can reduce the generation of lattice defects in the semiconductor device during the thermal oxidation process.

Method of manufacturing a semiconductor device having an oxidation process for selectively forming an oxide film

A wide high concentration P,type region is formed on the surface of an N,type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, holes generated at the outside of the cell region mostly flow through the P,type region and reach to an emitter electrode. Therefore, the flow amount of the holes does not concentrate on a channel P well for forming a channel region of the transistor device at the cell edge portion, whereby a ruggedness against a latch-up phenomenon can be improved.

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Nukata-gun, Japan

Yoshihiko Ozeki