Hitachi, Ltd.

Yoshihiko Kadowaki

Takashi Morikawa

Hiroya Okuda

An interface control system between a plurality of devices, such as a channel and an I/O device, includes sampling means for high speed sampling input control signals on an interface, a compare circuit for comparing a current sampled value sampled by the sampling means with an expected value for the input control signal previously prepared in the system and with a previously sampled value, respectively, to produce a compare equal signal when the sampled value is equal to the expected value, a matrix logic circuit responsive to the compare equal signal to set an output signal line corresponding to the expected value and an expected value for next sampling, and a circuit to produce a signal indicating an error condition or an exceptional condition when the sampled value is not equal to the expected value and the previous sampled value, to activate another logic circuit.

Interface control system for high speed processing based on comparison

Disclosed is a channel control system for controlling data transfers between a main storage and input/output devices. A plurality of channels are controlled by a common controller. The controller divides the processing for data transfer requests into a plurality of processing stages to allow the corresponding number of the channels to be controlled simultaneously by executing the processing for different channels separately at the divided individual processing stages.

Channel control system for controlling data transfer through a plurality

The channel device uses a first and a second data buffer therefore with first data buffer being used for data transfer to or from a main storage which has a data storage position determined by a data address indicating the data storage position in the main storage. The second data buffer used for data transfer to or from an I/O has a data storage position unrelated to the data address.

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Hadano, Japan

Yoshihiko Kadowaki