Nippondenso Co., Ltd.

Denso Corporation

Kabushiki Kaisha Toyota Chuo Kenkyusho

Yoshihiko Isobe

Makio Iida

Hiroyuki Yamane

Shoji Miura

Takeshi Yamauchi

Kazuo Akamatsu

Hidetoshi Muramoto

Atsushi Komura

Tooru Yamaoka

Tetsuo Fujii

Hiroyuki Ban

Yasunori Taga

Kazuhiko Sugiura

Hisanori Yokura

Mikimasa Suzuki

Kiyoshi Yamamoto

Takeshi Ohwaki

Makoto Ohkawa

Eishi Kawasaki

Hideya Yamadera

Masahiro Ogino

Hisayoshi Ooshima

Masami Saito

Hirofumi Abe

Katsuyoshi Oda

Kanemitsu Terada

Keizou Kajiura

A physical sensor includes: a substrate having a silicon layer, an oxide film and a support layer; and a sensor portion having movable and fixed electrodes and a lower electrode. The movable electrode is supported by a beam on the support layer. The fixed electrode faces the movable electrode. The lower electrode is disposed on the support layer and faces the movable electrode. The physical sensor detects horizontal physical quantity based on a capacitance between the movable and fixed electrodes, and vertical physical quantity based on a capacitance between the movable and lower electrodes. The beam includes vertical and horizontal beams. The thickness of the vertical beam is smaller than the thickness of the horizontal beam.

Physical sensor

A semiconductor pressure sensing apparatus includes a metallic stem having a diaphragm and a semiconductor sensor bonded to the diaphragm. The semiconductor sensor includes a gauge section and first and second bonding pads. The gauge section is configured to be deformed according to a deformation of the diaphragm. The first and second bonding pads are respectively connected to different positions of the gauge section so that an electrical resistance between the first and second bonding pads can change with a change in the deformation of the diaphragm. The gauge section is formed to a semiconductor layer of an silicon-on-insulator substrate. The semiconductor sensor is directly bonded to the diaphragm by activating contact surfaces between the semiconductor sensor and the diaphragm.

Semiconductor sensor for measuring a physical quantity and method of manufacturing the same

A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cmor less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.

Method of manufacturing semiconductor device

A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.

Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime

The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film , a titanium layer , a titanium nitride layer that serves as the barrier layer, an aluminum alloy wiring layer and a protective film are formed on top of the silicon substrate to compose the electrode structure. In this case, a distortion relaxation layer , with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer and the aluminum alloy wiring layer . Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.

Electrode for semiconductor device and method for manufacturing same

An MIS transistor fabricated in a manner that minimizes the occurrence of leak currents and that improves overall transistor performance by minimizing variation in location of the transistor source and drain during fabrication thereof. A gate electrode is first fabricated on a substrate. Next, a thermal oxide layer is formed on a side of the gate electrode. A masking process is then performed with the thermal oxide layer to form a source and a drain. A silicon oxide layer is then deposited over the gate electrode, the source and the drain. An etching process is performed on the silicon oxide to form a side wall oxide film over the thermal oxide layer on the side of the gate electrode and to expose surfaces of the gate electrode, the source and the drain. A metal film is then deposited over the gate electrode, the source and the drain and is heat treated to form a metal silicide film on the exposed surfaces of the gate electrode, the source and the drain. The side wall oxide film functions to disperse the metal silicide film as it is deposited to electrically separate the gate electrode, the source and the drain, thereby preventing a leakage current from occurring.

Insulated gate transistor with leakage current prevention feature

A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.

Semiconductor device having thin film resistor and method of producing same

In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Accordingly, in the high-voltage transistor, an electric field produced at a channel is relaxed. In the low-voltage transistor, a structure is made finer. A concentration of a well and an impurity amount implanted into a surface portion of a substrate are set to be identical with each other in all the transistors. Accordingly, the semiconductor device can be speedily manufactured at a high yield.

Semiconductor device including several transistors and method of manufacturing the same

The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 .mu.m, the number of Al voids with widths of over 0.3 .mu.m is practically reduced to 0.

Electrode for semiconductor device including an alloy wiring layer for

A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a mono-layer gate scheme to simplify the electrode wiring structure and to eliminate a current leakage problem of an insulating film between electrodes. A side and bottom of a semiconductor region, which is disposed directly below a capacity electrode section with a gate insulating film interposed therebetween that compose a control electrode, are isolated from another semiconductor region and semiconductor substrate by insulating films. Thus, a high programming control voltage which is not limited by a junction yield voltage between the semiconductor regions and semiconductor substrate may be applied. Due to that, an area of the capacity electrode section of a floating electrode may be considerably reduced.

Programmable non-volatile memory cell

A fuse fusible type semiconductor device capable of reducing energy required for fusing and a production method of the semiconductor device. In a semiconductor device equipped with a heat-fusible thin film resistor, the thin film resistor formed on a substrate 1 through an insulating film 2 is made of chromium, silicon and tungsten, and films 7 and 8 of a insulator including silicon laminated on the upper surface of the fusing surface, aluminum films 5 are disposed on both sides of the fusing surface and a barrier film 4. This semiconductor device is produced by a lamination step of sequentially forming a first insulating film 2, a thin film resistor 3, a barrier film 4 and an aluminum film 5 on a substrate 1 for reducing drastically fusing energy, an etching step of removing the barrier film 4 and the aluminum film 5 from the fusing region 31 of the thin film resistor 3, and an oxide film formation step of depositing the insulator including silicon films 7 and 8.

Semiconductor device equipped with a heat-fusible thin film resistor and

A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.

Method of making semiconductor device using a trimmable thin-film

A semiconductor device provided with a polycrystalline silicon resistor containing an impurity in a high concentration and having a resistance adjusted by a current conduction therethrough at a current density of a threshold value or more, which comprises: a polycrystalline silicon resistor containing a first impurity having a negative value of a temperature coefficient of resistance in a high impurity concentration region of said polycrystalline silicon resistor and a second impurity having a positive value of a temperature coefficient of resistance in a high impurity concentration region of the polycrystalline silicon resistor. A process for producing same is also disclosed.

Growing community of inventors

Toyoake, Japan

Yoshihiko Isobe