Other

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Yoshihiko Inoue

Masashi Horiguchi

Hiroshi Yoshioka

Masahito Suzuki

Manabu Ishimatsu

Hisashi Motomura

In a device including regular circuits and redundant circuits, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer as what constitutes the regular circuits and in the same direction, and at the same time the irrelievable wiring lines are arranged adjoining one another.

Semiconductor integrated circuit device

A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines. An address selecting circuit switches the defective word line to a redundant word line according to the evaluation result. The redundancy relief circuit then evaluates whether a refresh address added to the refresh address signal corresponds to a defective address, and during refresh, the address selecting circuit selects a normal or redundant word line according to the evaluation result in a preceding cycle.

Semiconductor memory having dynamic memory cells and a redundancy relief circuit

Growing community of inventors

Chikushino, Japan

Yoshihiko Inoue