Other

Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Yoshihiko Inoue

Hitoshi Miwa

Kayoko Shibata

Hiroaki Ikeda

Tatsuya Ijima

Atsushi Nakamura

Junji Yamada

Masayasu Kawamura

Yasushi Takahashi

Yoshitaka Kinoshita

Yoshihiro Sakaguchi

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x&#x2212;1 switch circuits to connect x&#x2212;1 data circuits to through silicon vias 1 to x&#x2212;1 in the group of n adjacent through silicon vias, activating n&#x2212;x switch circuits to connect n&#x2212;x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

Semiconductor device

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x&#x2212;1 switch circuits to connect x&#x2212;1 data circuits to through silicon vias 1 to x&#x2212;1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias.

A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

Stacked type semiconductor memory device and chip selection circuit

To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.

Stacked semiconductor device

Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

Growing community of inventors

Tokyo, Japan

Yoshihiko Inoue