Hitachi, Ltd.

Yoshihide Shirai

Yusuke Yamamoto

Mitsuaki Watanabe

An information processing apparatus includes a main CPU storage area and a sub-CPU storage area. The information processing apparatus further includes an FPGA capable of processing access to the main CPU storage area by a main CPU and access to the sub-CPU storage area by a second CPU in parallel. The FPGA has an FPGA control unit that performs processing. The FPGA control unit is configured to read prescribed data from an SPI device to the main CPU storage area and the sub-CPU storage area, update the prescribed data of the sub-CPU storage area when receiving an updating request from the sub-CPU, and read the prescribed data of the main CPU storage area to the main CPU when receiving a reading request from the main CPU.

Information processing apparatus, data control method, and recording medium for parallel access of processors to storage areas

A PCI card's HBA identifier table held in an IODC in an IO slot expansion unit is read and recorded on a PCIe switch register of a PCIe switch. After a server blade is powered on so that an EFI is activated, the EFI reads the HBA identifier table recorded on the PCIe switch register and updates an HBA identifier of an HBA mounted in each PCI card. The HBA mounted in the PCI card operates with the updated HBA identifier of the PCI card. Thus, even when the PCI card is replaced by a new PCI card because of failure or the like, the new PCI card can operate with the same HBA identifier as that before the replacement. Therefore, a user does not have to register the HBA identifier of the PCI card newly in a device connected to the PCI card.

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Hadano, Japan

Yoshihide Shirai