Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Yoshihide Komatsu

Takashi Hirata

Hironori Akamatsu

Satoshi Takahashi

Yutaka Terada

Tadahiro Yoshida

Yukio Arima

Hiroyuki Yamauchi

Hiroshi Suenaga

Tsuyoshi Ebuchi

Kohei Masuda

Shinichiro Nishioka

Toru Iwata

Osamu Shibata

Yoshiyuki Saito

Junji Nakatsuka

Takefumi Yoshikawa

Shinya Miyazaki

Koichi Sugimoto

Hirokazu Sugimoto

Yuji Yamada

Michiyo Yamamoto

Tsuyoshi Hiraki

Makoto Miyake

Masashi Suzuki

Satoshi Hori

An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.

Interchannel skew adjustment circuit

In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.

Driver circuit, receiver circuit, and method of controlling a communications system including the circuits

To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal. A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller. Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.

Interface circuit and interface system

A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.

Data transmission system capable of transmitting interrupt signal without interrupt gate period

A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.

Hybrid data transmission circuit

An AC-coupled interface circuit on a semiconductor integrated circuit apparatus performing a bidirectional data transfer via a differential transmission line includes a differential driver, a differential receiver and a potential setting section. The differential driver includes a pair of output terminals connected to a pair of signal lines. The differential receiver includes a pair of input terminals connected to the pair of signal lines. In a data transmission operation, the differential driver converts transmit data to a differential signal to output the differential signal. In a data reception operation, the differential receiver receives a differential signal transferred to the pair of signal lines and converts the differential signal to receive data. The potential setting section sets a potential of the pair of signal lines to a predetermined stable potential before the differential signal is transferred to the pair of signal lines.

AC-coupled interface circuit

A calibration circuit () adjusts at least one of one of a charging current of a charge pump circuit () and a capacitance value of a filter capacitor in a loop filter circuit () and a gain of a voltage controlled oscillator (), depending on a frequency of a reference clock signal input to a calibration circuit ().

Spread spectrum control PLL circuit and its start-up method

A circuit for detecting whether an intermittent clock waveform signal of 50 MHz is received or not includes an offset receiver, a charge pump, a capacitor and a hysteresis comparator. A circuit for detecting whether a random data waveform signal of 500 MHz is received or not includes an offset-less receiver, a transition counter, a delay circuit and an AND circuit. An OR circuit outputs as a signal detection signal a signal indicating the OR operation result of respective outputs of the hysteresis comparator and the AND circuit.

Signal detector

In data communication apparatus for communicating with another data communication apparatus via cables, when a power supply voltage applied to the data communication apparatus drops and the application of the power supply voltage is stopped, a power-supply-voltage-drop detecting circuit immediately detects the drop in the power supply voltage, thereby detecting the stop of application of the power supply voltage. When the stop of the power supply is detected, a stop signal outputting circuit outputs a communication stop signal to said another data communication apparatus. Accordingly, when power supply is stopped in one of the two pieces of data communication apparatus, it is possible to prevent a malfunction from occurring in the other data communication apparatus.

Method of stopping data communication of a communication apparatus based on a detection of a power supply voltage drop

The delay characteristic of a chip under test on which a function test is performed first is detected by performing an edge search for stabilizing the test without awaiting the delay characteristic to be stabilized and the result of detection is stored in a memory. By using the delay characteristic stored in the memory, the function test is performed repeatedly on the chip under test till NG (FAIL) occurs. When NG occurs, the function test is performed repeatedly till the NG count of the chip under test reaches a first specified number. If the NG count exceeds the first specified number, the foregoing process is repeated starting from the edge search. If the NG count reaches a second specified number, the chip under test is determined to be defective and the test is ended.

Method for testing semiconductor chips and semiconductor device

The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing inputting/outputting to/from a tester at low speed. The test circuit comprises a PLLwhich divides the frequency of a test clock input from the tester to generate a PLL clock CKp, a FIFOwhich stores input data input from the tester on the test clock and outputs the data on the PLL clock CKp, an encoderwhich distributes bits of the input data, a driverwhich transmits the output signal from the encoderto the outside, a PLLwhich divides the frequency of the test clock to generate a PLL clock CKp, a decoderwhich arranges the bits of the signal received by a receiver

Transmission device, reception device, test circuit, and test method

A current driver circuit has a current driver and a current compensation circuit. The current driver has a current source transistor connected to a power source potential level, while it is coupled to a pair of transmission lines. The current compensation circuit is coupled to the output side of the current source transistor for the compensation of an output current from the current driver in response to a common mode potential of the pair of transmission lines.

Current driver circuit

A network apparatus is provided, which allows another network apparatus to recognize the disconnection with reliability, if a power supply to the network apparatus is interrupted. A control unit operating with a first power supply outputs a first signal, which is level-converted and supplied as a second signal to an intermediate potential supply unit operating with a second power supply. In the intermediate potential supply unit, a switch receives a reset signal as a switch signal and outputs, when the power supply is interrupted, a ground potential to a driver instead of the second signal. As a result, an intermediate potential supplied to a cable is forcibly set to the ground potential.

Network apparatus

First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.

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Osaka, Japan

Yoshihide Komatsu