Fujitsu Corporation

Yoshiharu Mitono

Tetsu Tanizawa

Hiromu Enomoto

Yasushi Yasuda

Hitoshi Omichi

Hitoshi Ohmichi

Taketo Imaizumi

Takeshi Fukuda

Tadashi Kiriseko

Hiroshi Ohta

A semiconductor integrated circuit including at least one conventional inner cell region and an outer cell region. The outer cell region comprising a plurality of outer cells. Each outer cell is comprised of circuit elements for achieving a predetermined logic function, in addition to circuit elements for achieving the conventional buffer function of an outer cell. Further, two or more adjacent outer cells are connected each other and act as an independent circuit so as to form a macro-cell.

Gate array semiconductor integrated circuit

In an output transistor of transistor-transistor logic (TTL) circuits, an output transistor of TTL is provided with, in a region between a p-type base region and the p-type semiconductor substrate on which a TTL circuit is fabricated, a p.sup.- diffusion which causes carriers stored in the base region when the output transistor is switched from ON state to OFF state to be discharged quickly. When the output transistor is OFF, the p.sup.- diffusion is pinched off and no current flows. Thus, when the output transistor is switched from OFF state to ON state, the output voltage changes sharply. Because of this, the switching speed of the TTL is improved. In another embodiment, a p.sup.- region is formed between a p-type base region and p.sup.+ isolation diffusion, and an n.sup.+ diffusion is formed to cover at least one part of the p.sup.- diffusion and is connected to an n-type collector region. In another embodiment, a p-type base region extends to the p.sup.+ isolation diffusion, and an n.sup.+ diffusion is formed in a region between the base region and the isolation diffusion and is connected to an n-type collector region.

Semiconductor device with a means for discharging carriers

In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.

Semiconductor gate array device having an improved interconnection

An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip and which comprises an inner cell array including a plurality of inner cells, an outer cell array including a plurality of outer cells formed around the inner cell array, a power supply portion having one or more outer power supply lines, and a plurality of inner power supply lines connected to the outer power supply lines and formed on the inner cell array. The ratio of the pitch length of the outer cells to the pitch length of the inner power supply lines or the inner cells is determined by the ratio of two integers. In the integrated circuit device, at least one set of an outer cell, and an inner cell which are arranged in a predetermined positional relation, is formed a plurality of times along a side of the semiconductor chip.

Integrated circuit having predetermined outer to inner cell pitch ratio

In an integrated circuit manufactured by the master slice method, the feeder line for supplying electric power to a unit-cell array is gradually narrowed in width from the periphery to the middle of the array. As a result, sufficient voltage is supplied to the unit-cells at the middle of the IC and an area of an interconnecting domain for connecting the unit-cells is expanded.

Integrated circuit manufactured by master slice method

A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

Logic circuit with improved switching

A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.

Schmitt trigger circuit with low input current

A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.

Structure for and method of manufacturing a semiconductor device by the

A semiconductor device including a diode and a bipolar transistor which are connected to each other and formed in an isolated area of a semiconductor layer has a diffused region formed between a base region of the bipolar transistor and a formation region of the diode across the isolated area. The diffused region has the same conductivity type as that of the base region, so that a PNPN diode effect does not occur.

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Tokyo, Japan

Yoshiharu Mitono