Fujitsu Corporation

Fujitsu Vlsi Limited

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Spansion Llc.

Yoshiharu Kato

Satoru Kawamoto

Kazufumi Komura

Isamu Kobayashi

Yoshihiro Takemae

Takashi Hatano

Masami Nakashima

Toshio Ogawa

Yoshihiro Watanabe

Yoshinori Okajima

Satoshi Kakuma

Shiro Uriu

Masami Murayama

Kenichi Okabe

Yoshihiro Uchida

Mikio Nakayama

Jun Itoh

Yasuhiro Aso

Hidenori Nomura

Akihiro Iwase

Naoyuki Izawa

Jin Abe

Eiji Ishioka

Hiroshi Nishida

Noriko Samejima

Shinichiro Ikeda

Shigeru Sekine

Ryouzi Takano

Satoshi Esaka

Miyuki Kawataka

Yoshiyuki Karakawa

Fumio Hirase

Ryo Takajitsuko

Shinichi Araya

Tetsuhiko Endoh

Yasuhiro Nishikawa

Shinji Nagai

Hidetoshi Iwasa

Kiyofumi Mitsuze

Nobuyuki Tsutsui

Nobuyoshi Wakasugi

Yoshihisa Tsuruta

Atsushi Kagawa

Hiromi Yamanaka

Atsuko Suzuki

Shouji Kohira

Motoki Mizutani

Tomio Nakano

Makoto Yasuda

Akira Takashima

Takashi Nara

Sumie Morita

Fumihiko Taniguchi

Kenji Nagai

Tetsuya Hiraoka

Kazuyoshi Arimura

Shigemasa Ito

Makoto Niimi

Gen Tsukishiro

Kiyohumi Mitsuze

Toyonobu Yamada

Eisaku Itoh

Yoshio Morita

Yoshichika Nakaya

Yasusi Kobayasi

Masataka Sakai

Nobuyoshi Nakaya

Kouji Ishino

Takahiro Yokoyama

Kazushi Kodera

Shigeki Goto

Yasusi Kobayashi

A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor.

Semiconductor device and voltage divider

A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.

Fuse

A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.

Memory interface circuit, memory interface method, and electronic device

An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DCand DCproduce delay data strobe signals IDQSand IDQSdelayed by delay times DTand DT. Outputted as a reverse signal from the inverter INV, is a reverse data strobe signal RIDQSin response to the delay data strobe signal IDQS, and delayed by an allowable delay time IT. Inputted into the NAND gate ND, are the reverse data strobe signal RIDQSand the delay data strobe signal IDQS. When, in comparison with the phase of the delay data strobe signal IDQS, the phase of the delay data strobe signal IDQSis delayed by the allowable delay time IT or more, a pulse signal PLis not outputted from the NAND gate ND

Semiconductor device and method of testing the same

The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

Semiconductor memory device, refresh control method thereof, and test method thereof

A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

Memory system including nonvolatile memory and volatile memory and operating method of same

This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.

Interface circuit and control method thereof

An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DCand DCproduce delay data strobe signals IDQSand IDQSdelayed by delay times DTand DT. Outputted as a reverse signal from the inverter INV, is a reverse data strobe signal RIDQSin response to the delay data strobe signal IDQS, and delayed by an allowable delay time IT. Inputted into the NAND gate ND, are the reverse data strobe signal RIDQSand the delay data strobe signal IDQS. When, in comparison with the phase of the delay data strobe signal IDQS, the phase of the delay data strobe signal IDQSis delayed by the allowable delay time IT or more, a pulse signal PLis not outputted from the NAND gate ND.

A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.

Intra-station control system for connectionless communications system

It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k&#x2212;1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

Semiconductor memory device and method of controlling the semiconductor memory device

Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.

Signal interface

There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CCselects a memory chip CCan internal circuit of a select circuitis changed by a switch signal SWSIn this case, the changeover is made so that a select signal Soutputted from an internal circuitis inputted to a predetermined memory terminal of the memory chip CCThe select signal Sis inputted to the corresponding predetermined memory terminal of the memory chip CCand thereby, the memory chip CCis activated, and set to a state capable of inputting and outputting control signalstoThe control signalstoare assigned to control terminals Pto Pafter being hanged by the select circuitin signal sequence corresponding to terminal array sequence of memory terminalstoof the memory chip CC

Memory control device and memory control method

A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

Test method and test circuit for electronic device

A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k&#x2212;1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

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Kasugai, Japan

Yoshiharu Kato