Nec Corporation

Yoshiharu Aimoto

Tohru Kimura

Yoshikazu Yabe

Masato Motomura

Tadahiko Sugibayashi

Koichi Takeda

Muneo Fukaishi

Noritsugu Nakamura

Masakazu Yamashina

A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.

High-speed memory system

A dynamic memory including a first sense amplifier circuit directly connected to a bit line of a memory cell, a second sense amplifier directly connected to a data input/output circuit, a switching circuit connected between the first sense amplifier circuit and the second sense amplifier circuit. In a reading operation, the switching circuit is controlled to separate the first sense amplifier circuit and the second sense amplifier circuit from each other after data is read out from the memory cell, so that the read-out data is amplified by the second sense amplifier circuit and outputted from the second sense amplifier circuit to an external of the memory. On the other hand, the first sense amplifier circuit amplifies the read-out data and writes back the read-out data to the memory cell. In the writing operation, the switching circuit is controlled to interconnect the first sense amplifier circuit and the second sense amplifier circuit to each other, so that data to be written from an external is written into the memory cell through the first and second sense amplifier circuits.

Dynamic memory with increased access speed and reduced chip area

A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed with an application of a data compressor within the compression/decompression section, and compressed data-write with respect to the memory section is performed with an application of a data decompressor within the compression/decompression section. Owing to this structure, even when a data bandwidth is physically the same as in the conventional case, it is practically possible to achieve a larger data bandwidth in use.

Memory integrated circuit and main memory and graphics memory systems applying the above

A semiconductor memory device includes a pair of data lines, a precharging and equalizing circuit, a setting circuit and a data write circuit. The precharging and equalizing circuit is provided between the data lines to equally precharge the data lines to a first voltage in response to a precharge and equalize signal. The setting circuit is provided between the data lines to set one of the precharged data lines to a second voltage in response to data signals. The second voltage is lower than the first voltage. Also, a data Is written to a memory cell based on the second voltage of the one precharged data line and the first voltage of the other precharged data line. The data write circuit supplies the data signals to the setting circuit based on the data.

Semiconductor memory device with less power consumption

A random access memory device includes a plurality of memory blocks, a memory block selecting circuit and a column decoder. Each memory block comprise a memory cell array including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells, and a peripheral circuit including sense amplifiers which amplify data read out onto bit line pairs when a memory block select signal for a particular memory block is active to connect all memory cells contained in one row with associated bit line pairs. An access control circuit changes a block address and a column address while maintaining a row address unchanged, thus performing a rapid random access of memory cells contained in a common row over the memory blocks.

Semiconductor memory device for a rapid random access

A memory access system including a logic/control circuit, a memory, an address bus connecting the logic/control circuit and the memory and an address transition detector circuit provided on address lines constituting the address bus, the address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in the memory out of memory access signals transmitted from the logic/control circuit to the memory through the address lines and outputting a detection signal, and the logic/control circuit receiving input of the detection signal from the address transition detector circuit to temporarily stop its operation until the memory access is completed.

System for accessing dynamic random access memory where the

In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.

Data transfer apparatus with large noise margin and reduced power

A signal transmission circuit suitable for a memory device includes a signal generating section for generating a data signal from a power source, a pair of signal transmission lines for transferring the data signal by transferring signal charge associated by the data signal, an amplifying section for amplifying the data signal transferred by the signal transmission lines, and a precharge section for precharging the output of the signal generating section, the pair of signal transmission lines and the output of the amplifying section to a median potential level between the potential levels of the power source. The precharge section provides power saving as well as a larger noise margin.

Signal transmission circuit

In a semiconductor memory device comprising a plurality of memory cells which are arranged on a cell area defined by a first number of column signal lines and a second number of row signal lines, a row decoder produces a row selection signal through one of the second number of row signal lines. A serial access section includes a data register and serially accesses a part of the plurality of memory cells arranged along the one end of the second number of row signal lines. The plurality of memory cells are divided into a plurality of cell blocks. The data register is divided into a plurality of subword data registers each of which corresponds to each of the plurality of cell blocks. The serial access section accesses the plurality of cell blocks, in order, at a predetermined interval. Each of the plurality of subword data registers stores subword data in each of the plurality of cell blocks, in order, at the predetermined interval.

Serial random access memory device capable of reducing peak current

A dual port memory has a plurality of memory cell arrays. Plural bit lines for one word are divided into k groups each including m bit lines, and k data busses are commonly provided for all of the memory cell arrays. Bit selecting circuits control data transfer between the data busses and the memory cell arrays. A shift register circuit includes a plurality of partial shift registers which are serially connected with each other and each of which includes serially connected registers corresponding to the data busses. The shift register circuit carries out parallel data transfer between the data busses and each of the partial shift registers, and serial data transfer between one of the partial shift registers and an outside circuit. A dual port memory is provided in which the number of circuit elements and the surface size of memory chips can be reduced while maintaining a high speed of operation.

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Tokyo, Japan

Yoshiharu Aimoto