Denso Corporation

Nippondenso Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Yoshifumi Okabe

Akira Kuroyanagi

Masami Yamaoka

Yutaka Tomatsu

Mitsuhiro Kataoka

Koh Yoshikawa

Makoto Asai

Takeshi Fujii

Takaaki Aoki

Takeshi Fukazawa

Yoshihiko Ozeki

Masaki Koyama

Tomofusa Shiga

Norihito Tokura

Shigeki Takahashi

Hisanori Yokura

Kenji Kondo

Hajime Soga

Kimiharu Kayukawa

Masanori Miyata

Yasuaki Tsuzuki

Shoji Ozoe

Yasuo Ishihara

Yoshikazu Sakano

A semiconductor element test apparatus includes a first switch having a switching element, a coil, a second switch, a semiconductor element, a first rectifying element, and a second rectifying element. The first switch, the coil, and the second switch are connected in series to a power source. The semiconductor element is disposed to configure a loop path along with the coil and the second switch when the switching element is switched off. The semiconductor element has a diode element. A cathode electrode of the diode element is connected to a positive electrode of the power source. The second rectifying element is connected to the first rectifying element in series, and has a rectification direction opposite to a rectification direction of the first rectifying element. The first rectifying element and the second rectifying element configure, along with the coil, another loop path which is different from the loop path.

Semiconductor element test apparatus and semiconductor element test method

A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor

A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.

Vertical type semiconductor device and method for manufacturing the same

A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.

Semiconductor device and method of manufacturing same

In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.

Semiconductor device and method of manufacturing the same

A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

Method of manufacturing a vertical semiconductor device

A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Power semiconductor device

A vertical power MOSFET, which can improve a surge withstand voltage and a surge withstand voltage against a surge voltage from an inductance load L. The vertical power MOSFET has a plurality of unit cells. The unit cell is formed from a MOSFET that uses a p-type base layer at a sidewall of a rectangular U-groove as a channel portion. Each of the p-type base layer of each unit cell is connected each others Accordingly, it can restrain an impurity concentration of a corner portion (a portion positioned at a corner) of the rectangular p-type base layer from being decreased. Therefore, it can reduce the difference in distance from the end portion of the p-type base layer to the end portion of the depletion layer. As a result, it can improve the surge withstand voltage when a surge voltage is input from an inductance load L.

Vertical type MOSFET

Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode

A method of manufacturing of a semiconductor device having a thermal oxidation process for selectively forming an oxide film by a thermal oxidation, which can reduce the generation of lattice defects in the semiconductor device during the thermal oxidation process. A groove portion LOCOS oxide film is formed in a groove portion of a semiconductor substrate by first and second wet oxidation steps. At the first wet oxidation step, a thin oxide film is formed on an exposed surface of an epitaxial layer by performing a wet oxidation through an opening portion made of silicon nitride under an oxidation temperature of approximately 875&deg; C. At the second wet oxidation step, the oxidation temperature is risen to approximately 1050&deg; C. to advance the oxidation of the epitaxial layer to finally form the groove portion LOCOS oxide film having a thickness of approximately 950 nm. Lattice defects due to the dislocation is reduced by largely releasing the thermal stress generated at the semiconductor substrate portion corresponding to the edges of the groove portion LOCOS oxide film. Therefore, it can reduce the generation of lattice defects in the semiconductor device during the thermal oxidation process.

Method of manufacturing a semiconductor device having an oxidation process for selectively forming an oxide film

In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped-source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.

P-channel MOSFET semiconductor device having a low on resistance

In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.

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Anjo, Japan

Yoshifumi Okabe