Lam Research Corporation

Lam Research Corportation

Yoshie Kimura

Xiang Zhou

Ganesh Upadhyaya

Gowri Kamarthy

Chen Xu

Duming Zhang

Radhika C Mani

Mitchell Brooks

Alex Paterson

John Stephen Drewery

Tom A Kamp

Monica Titus

Noel Sun

Keith William Gaff

Eric A Pape

Yoko Yamaguchi

Nicolas Gani

Helene Del Puppo

Do Young Kim

Rohit Deshpande

Naveed Ansari

Haseeb Kazi

Jen-Kan Yu

Ting-Ying Chung

Si-Yi Yi Li

Kazi Sultana

Paul Raymond Besser

Bart Jan Van Schravendijk

Harmeet Singh

Qian Fu

Alexander Miller Paterson

Ying Wu

Meihua Shen

Baosuo Zhou

Gerardo Delgadino

Zhongkui Tan

Qing Xu

James Adams

Dengliang Yang

Yifeng Zhou

Hua Xiang

John Hoang

Qinghua Zhong

Yasushi Ishikawa

Yoko Yamaguchi Adams

Tae Won Kim

Gladys Lo

Juan Valdivia, Iii

Tony Zemlock

Zhaohong Han

Seokhwan Lee

Harald Orkorn-Schmidt

Zhuoxian Wang

Wenchi Liu

Colin Richard Rementer

Teng Hooi Goh

Weiye Zhu

A method for patterning a stack having a mask with a plurality of mask features is provided. A targeted deposition is provided, wherein the targeted deposition comprises a plurality of cycles, wherein each cycle comprises flowing a precursor to deposit a layer of precursor and targeted curing the layer of precursor, comprising flowing a curing gas, flowing a modification gas, forming a plasma from the curing gas and modification gas, and exposing the layer of precursor to the plasma providing a targeted curing, wherein plasma from the curing gas cures first portions of the layer of precursor and plasma from the modification gas modifies second portions of the layer of precursor, wherein the modification of the second portion reduces curing of the layer of precursor of the second portions of the layer of precursor. The stack is etched through the targeted deposition.

Method for etching features using a targeted deposition for selective passivation

Provided herein are methods and systems for reducing roughness of EUV resists and improving etched features. The methods may involve depositing a thin film on a patterned EUV resist having a stress level that is less compressive than a stress level of the patterned EUV resist. The resulting composite stress may reduce buckling and/or bulging of the patterned EUV resist.

Reducing roughness of extreme ultraviolet lithography resists

Systems and methods for synchronization of radio frequency (RF) generators are described. One of the methods includes receiving, by a first RF generator, a first recipe set, which includes information regarding a first plurality of pulse blocks for operating the first RF generator. The method further includes receiving, by a second RF generator, a second recipe set, which includes information regarding a second plurality of pulse blocks for operating a second RF generator. Upon receiving a digital pulsed signal, the method includes executing the first recipe set and executing the second recipe set. The method further includes outputting a first one of the pulse blocks of the first plurality based on the first recipe set in synchronization with a synchronization signal. The method includes outputting a first one of the pulse blocks of the second plurality based on the second recipe set in synchronization with the synchronization signal.

Synchronization of RF generators

Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.

Atomic layer deposition and etch in a single plasma chamber for critical dimension control

Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

Atomic layer deposition and etch for reducing roughness

A gas delivery system for a substrate processing system includes a first manifold and a second manifold. A gas delivery sub-system selectively delivers gases from gas sources. The gas delivery sub-system delivers a first gas mixture to the first manifold and a second gas mixture. A gas splitter includes an inlet in fluid communication with an outlet of the second manifold, a first outlet in fluid communication with an outlet of the first manifold, and a second outlet. The gas splitter splits the second gas mixture into a first portion at a first flow rate that is output to the first outlet and a second portion at a second flow rate that is output to the second outlet. First and second zones of the substrate processing system are in fluid communication with the first and second outlets of the gas splitter, respectively.

Gas delivery system

A method for etching a substrate includes performing, in a plasma chamber, a first etch of a substrate material using a plasma etch process. The first etch forms features to a first depth in the material. Following the first etch, the method includes performing, in the plasma chamber without removing the substrate from the chamber, an atomic layer passivation (ALP) process to deposit a conformal film of passivation over the mask and the features formed during the first etch. The ALP process uses a vapor from a liquid precursor to form passivation over the features and the mask. The method further includes performing, in the plasma chamber, a second etch of the material using the plasma etch process. The conformal film of passivation is configured to protect the mask and sidewalls of the features during the second etch. A plasma processing system also is described.

Integrated atomic layer passivation in TCP etch chamber and in-situ etch-ALP method

Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.

Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Internal plasma grid applications for semiconductor fabrication

A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber

A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

Air gap spacer integration for improved fin device performance

Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

Controlling CD and CD uniformity with trim time and temperature on a wafer by wafer basis

Growing community of inventors

Castro Valley, CA, United States of America

Yoshie Kimura