Nippon Telegraph and Telephone Public Corporation

Takeda Riken Kogyo Kabushiki Kaisha

Takeda Riken Co., Ltd.

Yoshichika Ichimiya

Tsuneta Sudo

Masao Shimizu

Shigeru Sugamori

Hiromi Maruyama

Katsumi Shimada

Susumu Sumida

Takashi Tokuno

Toshiaki Wakita

Turo Takehisa

A central processing unit is cascade-connected with a plurality of I/O units, and a bus interconnecting them comprises a plurality of data lines for transmitting a control command signal, an address signal and a data signal on a time shared basis, a plurality of tag lines, each transmitting a tag signal indicating which one of the signals is provided on the data lines, and a clock line for transmitting a clock signal for these signals.

I/O Control system for data transmission and reception between central

A semiconductor memory test pattern generating apparatus in which an instruction memory is read out, assigning an address by a program counter, and instructions thus read out are decoded and executed to generate a test pattern. A start address and a stop address and index data indicating the number of times of executing an area defined by the start and stop addresses are stored in a loop memory. During the operation of the program counter the start and stop addresses and the index data are read out from the loop memory and loaded in a register group. When the program counter coincides with the loaded stop address, the setting of the program counter to the loaded start address is executed by the number of times indicated by the loaded index data, and in the last execution the next address of the loop memory is read out.

Semiconductor memory test pattern generating apparatus

Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

Logical waveform generator

Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

High speed data logical comparison device

A plurality of low-speed memories having stored therein a plurality of patterns and first and second high-speed memories of higher operating speed than the low-speed memories are provided. One of the first and second high-speed memories is read to obtain output patterns and, at the same time, the plurality of low-speed memories are simultaneously read and the read-out data are successively written in the other high-speed memory alternately with each other. Upon completion of pattern generation from the one high-speed memory, pattern generation from the other high-speed memory is achieved.

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Tokorozawa, Japan

Yoshichika Ichimiya