Sanyo Electric Co., Ltd.

Yoshichika Hirao

Nobukazu Hosoya

Naoki Kaise

Takaaki Ishii

Tadashi Amino

Kazunori Nohara

Yasuyuki Ikeguchi

Takeshi Higashino

Toru Kirimura

Toru Sasaki

Ryoji Nakanishi

Tooru Sasaki

Koji Muraoka

Hidehiro Ugaki

Kenji Hyakutake

A projection type video display has a sensor which includes an image pick up device to take a projected image and the projection type video display projects an adjustment image to automatically implement the focus adjustment and the keystone distortion correction on the basis of output of the sensor.

Projection type video display

At the time of manual adjustment, a motor driving signal corresponding to a user's key operation is fed to a focusing motor from a microcomputer through a switch. At the time of automatic adjustment, the switch selects a motor driving signal from a sensor and feeds the selected motor driving signal to the focusing motor. The sensor contains a dedicated microcomputer. The dedicated microcomputer samples an image pick-up signal of a CCD line sensor in the sensor to generate contrast data, and automatically drives the focusing motor, to automatically make focusing adjustment.

A microcomputer performs image drawing processing of a projection video for adjustment by an OSD (On-Screen Display) circuit when it detects the press of an adjustment command key. The projection video for adjustment is an image having a black-and-white area high in contrast formed therein. The projection video for adjustment is picked up by a CCD line sensor in a sensor. A microcomputer has its input an image pick-up signal from the CCD line sensor, to make focusing adjustment and trapezoidal distortion correction on the basis of the image pick-up signal.

Projection type video display and method of adjusting the same at factory shipping

In a projection type display device having an electrical trapezoidal distortion correcting function, there are provided detection means for detecting an angle of inclination in the vertical direction of an optical axis of the projection type display device toward a screen surface, and control means for controlling the display position of an on screen display image displayed in a screen on the basis of the angle of inclination detected by the detection means.

Projection type display device

A cooling fan controller controls a voltage for driving a cooling fan on the basis of a temperature detected by a temperature sensor. A first controller controls voltage for driving the cooling fan to a minimum voltage for starting the cooling fan. A second controller controls the voltage for driving the cooling fan to a driving voltage value corresponding to the detected temperature after the cooling fan is started. A relationship between the detected temperature in the voltage for driving the cooling fan is such that the higher the detected temperature becomes the larger the voltage for driving the cooling fan becomes. A predetermined minimum voltage for cooling fan control is lower than the minimum voltage for starting the cooling fan and a predetermined maximum voltage for cooling fan control is higher than the minimum voltage for starting the cooling fan.

Cooling fan controller and liquid crystal projector

Disclosed is a period measuring device comprising a clamping circuit to which a synchronizing signal in an input image signal is inputted, a comparator for removing noise in the synchronizing signal outputted from the clamping circuit, period measuring circuit for measuring the period of the synchronizing signal on the basis of the synchronizing signal obtained by the comparator, judging circuit for judging whether or not the period of the synchronizing signal which has been measured by the period measuring circuit is stable, and a control circuit for controlling, when the judging circuit judges that the period of the synchronizing signal is not stable, a threshold voltage of the comparator such that the period of the synchronizing signal is stabilized.

Device for measuring period of synchronizing signal and display device

A burst phase correcting circuit includes a first all-pass filter which receives a chrominance sign inputted from a terminal. A phase reference signal from an oscillator is applied to a first phase-comparator together with an output signal from the first all-pass filter, after the same is phase-shifted by 90 degrees by a first phase-shifter. A signal according to a phase difference of the both signals is outputted from the first phase-comparator and applied to the first all-pass filter via a first low-pass filter and a capacitor. Therefore, in the first all-pass filter, a delay time is varied in accordance with the phase difference between the chrominance signal and the phase reference signal. Therefore, a jitter component of the chrominance signal can be removed.

Burst phase correcting circuit

A frequency of a chrominance signal including a jitter component and separated from a color video signal is converted from a first frequency to a second frequency by first frequency converting device. Then, the chrominance signal which frequency is converted to the second frequency is converted to have the original frequency by second frequency converting device. Each of the first frequency converting device and the second frequency converting device includes a multiplier and a bandpass filter. One multiplier of the first and the second frequency converting devices and receives a frequency signal corresponding to a phase difference between a reference frequency signal and a color burst signal separated from the chrominance signal. As a result, the jitter component is removed from the chrominance signal either in the first or the second frequency converting. In the first and the second frequency converting devices and, the input signal and the output signal so widely differ from each other in frequency that the respective frequency components included in the output signal of the multipliers in the respective frequency converting device expend widely along an axis of a frequency. As a result, the bandpass filter in each frequency converting device is enabled to easily extract only a signal of a desired frequency component.

Circuit for removing jitter of chrominance signal and television set

A synchronizing signal separating circuit inverts and amplifies, in an inverter 12, a composite video signal received from a video amplifying circuit 100 through a coupling condenser 1. An output node B of the inverter 12 is connected to an input node A of the inverter 12 through a switch 14 and a bias resistor 10. A bias resistor 11 is connected between the input node A and a ground potential. An output of the inverter 12 is further inverted and amplified by an inverter 13 and outputted as a composite synchronizing signal and also supplied to a control input of the switch 14. As a result, the switch 14 is turned on in a synchronizing signal period, so that the coupling condenser 1 is charged with the output of the inverter 12 and also the electric charges of the coupling condenser 1 are discharged through the bias resistor 11 in other period than the synchronizing signal period. Therefore, irrespective of a APL of an inputted composite video signal, it is possible to maintain a level difference between a top level of the synchronizing signal and a separation level to be constant to correctly perform separation of the synchronization.

Synchronizing signal separating circuit separating synchronizing signal

A circuit for providing a signal phase locked to a horizontal synchronization signal included in a received video signal includes a first PLL loop (16, 44, 46; 16, 46', 204) and a second PLL or AFC loop (26, 44, 46; 26, 44, 46', 204). The first PPL loop has a plurality of lock ranges. The second PLL or AFC loop, which has an output characteristic with a single S curve, has one lock range large in width. The second PLL or AFC loop is supplied with a horizontal synchronization signal separated in a synchronization separating circuit via a bandpass filter. The first PLL loop is directly supplied with a horizontal synchronization signal extracted in the synchronization separating circuit. The first PLL loop shares a voltage controlled oscillator (46; 46') and a frequency divider (46; 204) with the second PLL loop or AFC loop. This phase synchronizing circuit further includes a circuit (48) for detecting synchronization/non-synchronization of an output of the frequency divider circuit with the horizontal synchronization signal separated/extracted in the synchronization separating circuit, and a switching circuit (42) for activating one of the first PLL loop and the second PLL or AFC loop in response to an output of this synchronization detector circuit.

Phase synchronizing circuit in video signal receiver and method of

A peak holding circuit comprises a capacitor for holding signal charges corresponding to a peak level of an input signal, and a current amplifier circuit comprising transistors connected in a triple darlington manner for supplying an output current corresponding to the held charges. An emitter of a transistor in the first stage out of the transistors connected in a darlington manner is connected to a collector of another transistor through which a collector cut-off current flows which is approximately equal to a collector cut-off current flowing through the transistor in the first stage. The other transistor has its emitter connected to ground. Therefore, the collector cut-off current flowing through the transistor in the first stage is cancelled, so that fluctuations in output current can be prevented even if a large reactive current is not allowed to flow through a transistor in the final stage out of the transistors connected in a darlington manner.

Peak holding circuit for a color television receiver

A television signal converter includes a CATV tuner having a channel converting function, a gain changing circuit for descrambling the output from the CATV tuner and the like, in order to convert a television signal such as a CATV signal formed by a scrambled video signal into a descrambled television signal of channel 3, for example. The descrambled channel 3 CATV signal outputted from the gain changing circuit includes noise in the reproduced audio signal since the audio carrier is influenced by gain changing. In the present invention, therefore, the audio signal is reproduced from an audio carrier extracted from the front stage of a gain changing circuit. Thus, the reproduced audio signal is released from noise caused by gain changing.

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Neyagawa, Japan

Yoshichika Hirao