Kabushiki Kaisha Toshiba

Yoshiaki Toyoshima

Akira Hokazono

Tatsuya Ohguro

Katsura Miyashita

Yukio Wada

Takeshi Matsunaga

Hiroshi Takakura

Hirohumi Shinagawa

Hiroyuki Hayashida

Masayuki Norishima

Tamao Eguchi

A semiconductor device includes a light-receiving element which is connected to a negative power supply and generates conductive carriers by receiving light, an amplifier transistor which is a depletion transistor and amplifies an electrical signal obtained by the conductive carriers, and a transfer gate transistor which is a depletion transistor and is controlled by a negative potential applied to a gate to electrically connect or disconnect the light-receiving element and the amplifier transistor.

Semiconductor device

An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages.

Electrical fuse with metal silicide pipe under gate electrode

An aspect of the present invention includes a first MOSFET having a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate, a first channel region formed immediately below the first gate electrode in the first semiconductor layer, a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer, a first epitaxial layer formed on the first diffusion layer, and a first silicide layer formed on the first epitaxial layer, and a second MOSFET having a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate, a second channel region formed immediately below the second gate electrode in the second semiconductor layer, a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer, and a second silicide layer formed on the second diffusion layer.

Method of manufacturing a semiconductor device

A programmable element includes a resistive element having a polysilicon film and a metal silicide film or metal film stacked on the polysilicon film. The electric resistance of the resistive element is changed by changing the composition of the metal silicide film or metal film or the chemical bond state using heat, thereby programming on the basis of the change in the electric resistance of the resistor.

Programmable element programmed by changes in resistance due to phase transition

Semiconductor device and method of manufacturing the same

A semiconductor device with digital and analog circuits has a structure for preventing noise penetration from the digital circuit to the analog circuit. The semiconductor device has a semiconductor substrate, first and second wells independently formed at a surface of the semiconductor substrate, the digital circuit formed at a surface of the first well, and the analog circuit formed at a surface of the second well. The specific resistance of the semiconductor substrate is at least 1000 times as large as the specific resistance of the first well. A conductive guard-ring may be formed in the surface of an area that is between the digital circuit and the second well or between the first well and the second well.

Semiconductor devices which have analog and digital circuits integrated on a common substrate

A semiconductor integrated circuit device comprises a semiconductor substrate; an input and output terminal (1) formed on the semiconductor substrate; an input and output circuit (2, 3) formed on the semiconductor substrate, connected to the input and output terminal (1), and having an output buffer (2) of CMOS FETs, supply voltages Vcc1 and Vcc2 being applied to the output buffer; a semiconductor integrated circuit formed on the semiconductor substrate and connected to the input and output circuit; and a circuit for preventing forward junction current from flowing from the input and output terminal (1) to the output buffer (2) when an input voltage exceeding the supply voltages is applied to the output buffer. In an integrated circuit device using a plurality of different supply voltages, it is possible to prevent an input voltage beyond the supply voltages from being applied to the input and output circuit. A voltage switching circuit (4) responsive to signals A and B supplied to an output buffer (2) is interposed between the output buffer (2) and a pad (1). When a voltage higher than the supply voltages is applied to the output buffer (2) from the outside, the substrate potential is determined to a value equal to or higher than the external voltage. Further, the voltage applied from the outside can be also lowered than the supply voltages of the output buffer, before applied to the output buffer.

Semiconductor integrated circuit device having circuitry for limiting

A mask for evaluation of an aligner includes, on a transparent substrate, a plurality of resistance measurement pattern blocks each including a plurality of resistance measurement patterns which have shapes identical to each other. Resistance values of respective measurement patterns of conductive film portions on a substrate exposed and formed by using a mask having a plurality of the same measurement patterns vary in dependency upon the accuracy of a lens, etc. of the aligner. Accordingly, this evaluation mask is used to carry out exposure process to etch a conductive film to measure resistance values of the conductive film portions to compare them to each other, thereby making it possible to carry evaluation of an aligner including evaluation of a lens therefor.

Mask for evaluation of aligner and method of evaluating aligner using

A semiconductor device comprises an element separating insulation film formed on a main surface of a silicon substrate, an insulation film formed to project from the edge portion of the element separating insulation film onto a part of a silicon region of the substrate and having a thickness smaller than the thickness of the element separating insulation film, a first metal silicide film formed to cover the element separating insulation film and the thin insulation film in the vicinity of the edge portion of the element separating insulation film, a second metal silicide film formed on the silicon region in the vicinity of the thin insulation film, and a third metal silicide film formed in the vicinity of the tip portion of the thin insulation film for connecting the first and and second metal silicide films.

Semiconductor device having an interconnected film with tapered edge

Formed on the element region of an n-type semiconductor substrate is a silicon oxide layer, on which a polysilicon layer is formed. Boron ions, p-type impurities, are then implanted into the polysilicon layer, from which boron diffuses into the element region via the silicon oxide layer, with the result that a p-channel region of the p-channel MOS transistor is formed.

Maufacturing method of semiconductor devices

The invention provides a semiconductor device and manufacturing method therefor which comprises: a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type provided on the surface of the substrate in a mutually electrically isolated arrangement, and a gate electrode provided on the surface of the substrate on the other side of an insulating film and the substrate surface including a channel region between these aforementioned regions; at least the drain region, of which the source and drain regions, consisting of: a first impurity diffusion region provided on the substrate surface in the vicinity of the end portion of the gate electrode; a second impurity diffusion region more highly doped than the first impurity diffusion region and provided in at least a portion of the surface of the aforementioned diffusion region adjacent the end portion of this first impurity diffusion region; and a third impurity diffusion region more highly doped than the second impurity diffusion region and provided on the substrate surface adjacent to the end portion of this second impurity diffusion region.

Growing community of inventors

Kashiwa, Japan

Yoshiaki Toyoshima