Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Semiconductor Limited

Yoshiaki Okuyama

Shinya Fujioka

Kaoru Mori

Hitoshi Ikeda

Akihiro Funyu

Jun Ohno

Atsushi Takeuchi

Yoshitaka Takahashi

Takahiko Sato

Tatsuya Kanda

Kotoku Sato

Tomohiro Kawakubo

Kota Hara

Waichiro Fujieda

Yasuyuki Eguchi

Nobumi Kodama

Katsuhiro Mori

Hiroyoshi Tsuboi

Yasuhiro Takada

Tatsuhiro Watanabe

Souichi Inaba

A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

Semiconductor memory, operating method of semiconductor memory, memory controller, and system

A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

Data transfer method and system

A semiconductor memory device includes a DRAM memory core circuit including a word line, a power supply circuit configured to operate in a selected one of a first state and a second state to generate a predetermined power supply voltage for provision to the DRAM memory core circuit, the power supply circuit consuming a larger electric current in the first state than in the second state, and a control circuit configured to control the power supply circuit such that the power supply circuit is shifted from the first state to the second state, and is then brought back to the first state during a period from activation of the word line to deactivation of the word line.

Semiconductor memory device with reduced current consumption

Column switches are disposed for sense amplifiers respectively and are selectively turned on according to a column address to connect the sense amplifiers to a common data line. A sense amplifier control circuit activates a sense amplifier activation signal to operate the sense amplifiers. During a test mode, the sense amplifier control circuit changes time interval from activation of a word line to the activation of the sense amplifier activation signal, according to the column address. Then, a time interval after data is read to a bit line from a test target memory cell until the corresponding sense amplifier starts an amplifying operation is made constant irrespective of the position of the memory cell. Consequently, the same test condition can be set for the memory cells irrespective of the memory cells' positions. Correct evaluation of operation margins of the memory cells is possible irrespective of the positions of memory cells.

Semiconductor memory and testing method of same

In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

Semiconductor memory

An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.

Semiconductor memory device

An oscillator generates a refresh request signal periodically. A storing circuit changes a stored value by a predetermined value in response to the refresh request signal and returns the stored value by one in response to a refresh operation. A store control circuit, when a state detecting circuit detects a change of an operational state of a semiconductor memory, increases or decreases the predetermined value which the storing circuit uses. A refresh decision circuit outputs refresh signals of a number corresponding to the stored value until the stored value returns to an initial value. This makes it possible to change the frequency of the refresh operations according to a change of the operational state without changing an oscillation cycle of the oscillator. Without unnecessary oscillation of the oscillator, it is possible to decrease a standby current of the semiconductor memory.

Semiconductor memory which performs the refresh operation internally and automatically without refresh commands from the exterior

A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

Semiconductor memory and burn-in test method of semiconductor memory

A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.

Semiconductor memory having test function for refresh operation

An arbiter judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit judges which of a normal memory cell and a redundancy memory cell is accessed, in accordance with each of the internal access request and the external access request. When the arbiter gives higher priority to the internal access request, the redundancy judgement circuit carries out redundancy judgement for the external access request during internal access operation. To prevent the malfunction of a memory core, a hold circuit holds redundancy judged result, and prevents the redundancy judged result for the external access request from being transmitted to the memory core that carries out the internal access operation.

Semiconductor memory automatically carrying out refresh operation

A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

Semiconductor memory having burst transfer function

A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.

Semiconductor memory apparatus simultaneously accessible via multi-ports

Semiconductor memory having burst transfer function and internal refresh function

A first switch operates in accordance with a control signal and receives an input signal. A voltage conversion circuit converts the input signal having a voltage and transmitted via the first switch to an output signal having a different voltage, and outputs the signal. A second switch connects an output node thereof to a voltage line supplied with a voltage which the voltage conversion circuit should output in accordance with the input signal. Therefore, even the input signal's voltage falling outside the range in which the voltage conversion circuit normally operates, the voltage that the voltage conversion circuit should intrinsically output is supplied to the output node via the second switch. Thus, reliable conversion of the input signal voltage is achieved, resulting in secure operation of the level shifter even during a low power supply voltage. This also prevents malfunction of the semiconductor integrated circuit incorporating such level shifters.

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Kawasaki, Japan

Yoshiaki Okuyama