Sakai Display Products Corporation

V Technology Co., Ltd.

Yoshiaki Matsushima

Nobutake Nodera

Takao Matsumoto

Shigeru Ishida

Ryohei Takakura

Kazuki Kobayashi

Taimi Oketani

Satoru Utsugi

Ryouhei Takakura

Michinobu Mizumura

Yuta Sugawara

Shinji Koiwa

Masakazu Tanaka

Ryo Murata

Takeshi Uno

Satoshi Michinaka

Kota Imanishi

Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

Thin film transistor, display device, and thin film transistor manufacturing method

Provided are a laser annealing apparatus, a laser annealing method, and a mask with which scan nonuniformity can be decreased. According to the present invention, all or some openings of a plurality of openings are configured so that a partial subregion of a prescribed region is irradiated with laser light. The plurality of openings are configured so that, between prescribed regions irradiated with laser light via a group of openings in one row arranged in a row direction and prescribed regions irradiated with laser light via a group of openings in another row arranged in the row direction, the number of times of laser light radiations in subregions having the same occupying region is the same, and at least two openings of a group of openings arranged in a column direction have different positions or shapes.

Laser annealing apparatus, laser annealing method, and mask

A laser irradiation apparatus includes a light source that generates a laser beam, a projection lens that radiates the laser beam onto a predetermined region of an amorphous silicon thin film deposited on each of a plurality of thin film transistors on a glass substrate, and a projection mask pattern provided on the projection lens and has a plurality of openings so that the laser beam is radiated onto each of the plurality of thin film transistors, wherein the projection lens radiates the laser beam onto the plurality of thin film transistors on the glass substrate, which moves in a predetermined direction, through the projection mask pattern, and the projection mask pattern is provided such that the openings are not continuous in one column orthogonal to the moving direction.

Laser irradiation apparatus, thin film transistor, and method of manufacturing thin film transistor

In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape. Thereafter, when a metal layer for the source electrode and the drain electrode is formed, the shape of the cleared portion, which is a recessed portion, is followed, thereby forming a depression in the metal layer. Consequently, the depression is used as an alignment mark, and the source electrode and the drain electrode are formed at appropriate positions on the upper side of the channel region.

Method for manufacturing thin film transistor and display panel

There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).

Display apparatus and method of manufacturing display apparatus

Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.

Thin film transistor and method of manufacturing thin film transistor

A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.

Method of manufacturing thin film transistor and thin film transistor

The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.

Thin film transistor and display panel

The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.

Method for manufacturing thin film transistor, thin film transistor and display panel

A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and a second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate that is disposed on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a slit is formed in a part or the whole of the peripheral edge portion of the second insulating film disposed on a further inner side than a position at which the second insulating film overlaps the sealing material. In addition, a slit formed in a peripheral edge portion of the first insulating film that corresponds to the sealing material is filled with a gate insulating film having a higher barrier property for gas and/or liquid than the first insulating film.

Liquid crystal panel

The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.

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Sakai, Japan

Yoshiaki Matsushima