Kabushiki Kaisha Toshiba

Yoshiaki Kitaura

Kazuya Nishihori

Kyoichi Suguro

Kazuhide Abe

Tomonori Aoyama

Shuichi Komatsu

Mayumi Morizuka

Kumi Okuwada

Yoshikazu Tanabe

Tadahiro Sasaki

Atsushi Kameyama

Masami Nagaoka

Hirotsugu Wakimoto

Naotaka Uchitomi

A MESFET of a GaAs semiconductor device having a p-pocket LDD structure is used for a high-frequency power amplifier of a mobile communication device, in order to decrease current consumption and to increase the continuous operating time of a battery. The high-frequency power amplifier is provided with a gate-bias adjusting feedback element between the drain and gate of the MESFET. Thus, even if there is a great difference between the filled and terminated potentials of the discharge voltage of the battery for supplying electric power to the amplifier, electric power can be supplied near the terminated potential for a long time, so that the mobile communication device can be continuously used for a long time.

High-frequency power amplifier and mobile communication device using same

A manufacturing method of compound semiconductor field effect transistor capable of enhancing a gate/drain withstand voltage includes a step of forming a channel layer by implanting ions into the surface of a semi-insulating compound semiconductor substrate and a step of performing a first thermal treatment for removing crystalline defects on the surface of the channel layer. This method also includes a step of forming a compound semiconductor epitaxial layer by use of an epitaxial method on a region covering the channel layer, a step of forming a gate electrode within a region on the epitaxial layer just above the channel layer and a step of forming a source region and a drain region in the substrate. A concentration of the impurity for forming the channel layer at an interface between the channel layer and the epitaxial layer is 45% or under of the highest concentration when forming the channel layer. A good interface between the channel layer and the epitaxial layer can be thereby obtained, and a transistor having the high-quality epitaxial layer can be also acquired.

Manufacturing method of compound semiconductor field effect transistor

A field effect transistor comprises: a first conductive type active layer formed on a surface region of a semiconductor substrate; first conductive type, source and drain regions formed on the semiconductor substrate on both sides of the gate electrode, the source and drain regions having a higher density of impurity than that of the active layer; and first conductive type, first and second impurity regions formed on the semiconductor substrate between a channel region below the gate electrode and the source region and between the channel region and the drain region, the first and second impurity regions having a depth, which is substantially the same as or deeper than that of those of the source region and the drain region, the first and second impurity regions having a density of impurity, which is higher than that of the channel region and lower than those of source region and the drain region. Thus, it is possible to provide a field effect transistor having a high power conversion efficiency, and it is possible to increase the drain efficiency and the yield as high as possible.

Field effect transistor and high-frequency power amplifier having same

An SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 nm) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

MMIC semiconductor device with WN.sub.x capacitor electrode

A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

Metal oxide capacitor with a WN.sub.X electrode

Growing community of inventors

Kawasaki, Japan

Yoshiaki Kitaura