Mitsubishi Denki Kabushiki Kaisha

Yoshiaki Katoh

Tokumichi Murakami

Naoto Kinjo

Koh Kamizawa

Hideo Ohira

Masatoshi Kameyama

A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Digital signal processor with conditional branch decision unit and

Digital signal processor system having host processor for writing

Digital signal processor having duplex working registers for switching

Address control and generating system for digital signal-processor

Digital signal processor

Growing community of inventors

Kanagawa, Japan

Yoshiaki Katoh