Oki Electric Industry Co., Ltd.

Yoshiaki Katakura

Yasuhiro Fukuda

Jun Kanamori

Akito Nishitani

In fabricating a capacitor portion of a semiconductor device, after forming an upper electrode, a resist pattern for forming a lower electrode is formed and etching processing of an insulating film layer and a first metal layer is carried out. Thus, the lower electrode and a wiring pattern can simultaneously be formed by etching the insulating film layer and the first metal layer after forming a resist pattern one time, without a resist pattern directly formed on the first metal layer.

Method of fabricating semiconductor device equipped with capacitor portion

Input/output protection circuit

An LDD MIS structure without a lightly-doped source region can be formed by the use of the conventional self-alignment technique. The structure includes in a silicon substrate a gate region, a heavily-doped drain region, a heavily-doped source region, and a lightly doped drain region. The gate region consists of a gate electrode and a side-wall spacer. The lightly-doped drain region is formed under the side-wall spacer, and in the silicon substrate.

Growing community of inventors

Kanagawa, Japan

Yoshiaki Katakura