Renesas Electronics Corporation

Nec Corporation

Yoshiaki Ishizeki

Hiroaki Shirai

Jou Kudou

A serial communication apparatus includes a slew rate control circuit, an output circuit, a detection circuit, and a switching circuit. The slew rate control circuit has a predetermined impedance, and supplies a constant current from an output according to an input signal. In the output circuit, first capacitance is charged and discharged by the constant current from the slew rate control circuit. The output circuit outputs a digital signal from an output terminal according to a drive voltage. The noise detection circuit detects noise propagated from the output terminal, and outputs a switching signal according to a detection result. The switching circuit switches an impedance of the slew rate control circuit to a value smaller than the predetermined impedance according to the switching signal.

Serial communication apparatus

According to the present invention, a small impedance detection circuit capable of accurately detecting the impedance of an object to be measured and an adjustment method of an impedance detection circuit can be provided. In the impedance detection circuit according to the present invention, an AC signal generator outputs an AC signal. A detection circuit, which is connected to a circuit to be measured, applies an AC signal to the circuit to be measured. Further, the detection circuit outputs a first signal corresponding to the composite impedance of the impedance of the circuit to be measured and a parasitic impedance. A correction circuit outputs a second signal in synchronization with the first signal. A subtraction circuit outputs a detection signal obtained by subtracting the second signal from the first signal.

Impedance detection circuit and adjustment method of impedance detection circuit

In a bit clock generation circuitry, a T/2 pulse generator includes a monostable multivibrator triggered by an edge of an input PCM data signal and controlled by a time constant adjusting signal so as to generate a pulse signal having its pulse width adjusted in accordance with the time constant adjusting signal. In response to a pulse signal generated by the monostable multivibrator, a D-type flipflop latches the input PCM data signal for generating a delayed data signal delayed from the input PCM data signal by T/2. An exclusive-OR means receives the input PCM data signal and the delayed data signal for generating a T/2 pulse signal.

Bit clock regeneration circuit for PCM data, implementable on integrated

A phase-error detecting circuit for detecting a phase error of an output signal of the VCO in a QDPSK demodulating circuit in accordance with the Costas loop method is disclosed. The phase-error detecting circuit comprises a first circuit which generates a first product (P.times.Q) of a first demodulated signal (P) and a second demodulated signal (Q) of a QPSK signal. A second circuit generates the difference of the squares (P.sup.2 -Q.sup.2) of the first and second demodulated signals. A third circuit receives both the first product (P.multidot.Q) generated by the first circuit and the difference (P.sup.2 -Q.sup.2) generated by the second circuit and generates the product of the first product (P.multidot.Q) and the difference (P.sup.2 -Q.sup.2). The first circuit includes a first quadratic multiplier for generating the first product. The second circuit includes second and third quadratic multipliers, a phase-reversing mechanism for reversing the phase of the signal (Q), and an adding mechanism. The second quadratic multiplier generates the square of the first signal (P.sup.2). The third quadratic multiplier multiplies the second signal and the phase-reversed second signal generating (-Q.sup.2 ). The adding mechanism adds (P.sup.2) and (-Q.sup.2).

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Kanagawa, Japan

Yoshiaki Ishizeki