Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Yoshiaki Hisamoto

Kazunari Hatade

Atsushi Narazaki

Hiroshi Yamaguchi

Toshihiro Nakajima

Hitoshi Uemura

Kozo Yamagami

A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

Power semiconductor device having an active region and an electric field reduction region

A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

Semiconductor device with peripheral base region connected to main electrode

A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3&#xd7;10/cmwith an energy of approximately 50 KeV to a depth of approximately 0.5 &#x3bc;m, and an nbuffer layer with phosphorus injected in an amount of approximately 3&#xd7;10/cmwith an energy of 120 KeV to a depth of approximately 20 &#x3bc;m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1&#xd7;10/cmto a depth of approximately 32 &#x3bc;m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Semiconductor device

A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base region and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

Semiconductor device with increased withstand voltage

A semiconductor device has an enhanced di/dt tolerance and a dv/dt tolerance without increasing an ON resistance. An underpad base region is provided on a region in an upper main surface of a semiconductor substrate which is provided under a gate pad, and the underpad base region is not connected to a source electrode and is not coupled to a main base region connected to the source electrode. The underpad base region is brought into a floating state.

Semiconductor device having enhanced di/dt tolerance and dV/dt tolerance

A Zener diode is provided in a chip periphery portion which entirely surrounds at a periphery a unit cell portion and a gate pad portion along first to fourth directions. The Zener diode has an N -P-N -P-N structure consisting of an N type layer, a P type layer, an N type layer, a P type layer, and an N type layer, in which these layers extend along the first to fourth directions. With this structure, a power semiconductor device achieves a higher electrostatic strength by (1) a reduction in on-state resistance through enlargement of an effective cell region by downsizing the gate pad, and (2) an improvement in current-voltage characteristic of the Zener diode through an increase in PN junction width.

Power semiconductor device containing at least one zener diode provided in chip periphery portion

In order to prevent an etch-down phenomenon in a gate electrode (106), a source electrode (108) is connected to an upper major surface of a semiconductor substrate (160) through openings (112, 112a) of a protective film (107), while a gate wire (109) is connected to the gate electrode (106) through an opening (111). The opening (112, 112a) are formed by dry etching, whereby the source electrode (108) is reliably insulated from the gate electrode (106). On the other hand, the opening (111) is formed by wet etching, whereby the gate electrode (106) is not etched down. Thus, it is possible to prevent short-circuiting defectiveness across the gate electrode (106) and the semiconductor substrate (160) resulting from an etch-down phenomenon of the gate electrode (106) while guaranteeing electrical insulation between the gate electrode (106) and the source electrode (108).

Method of fabricating insulated gate semiconductor device

An insulated gate bipolar transistor comprises an insulation film (7) formed on a channel region (6) and a gate electrode (8) formed on the insulation film (7). The end portion of the gate electrode (8) has recesses so that the gage electrode (8) covers part of the channel region (6) at a predetermined rate. The rate may be made small to increase a channel resistance so that an excessive current at the time of load short-circuiting can be suppressed. In place of the recesses, a step structure may be provided. Further the gate electrode (8) may cover part of the channel region (6) without providing the recesses.

Insulated gate bipolar transistor and method of fabricating the same

An electrode region, which is formed in an active region in a semiconductor element forming region isolated by dielectric isolation, for example, comprises a polycrystalline semiconductor layer containing a predetermined conductivity type impurity in high concentration and a diffusion layer of the sam conductivity type formed in a periphery of the polycrystalline semiconductor layer. The polycrystalline semiconductor layer can be easily and correctly increased in impurity concentration and increased in high workability in thickness. Thus the semiconductor device having an electrode region of high concentration in desired thickness can be implemented.

Method of manufacturing a semiconductor device having a polycrystalline

A gate turn-off thyristor including N-type emitter regions (4) formed in part in the surface layer of a P-type base layer (3), and P.sup.+ layer regions (10) of a high impurity concentration formed immediately beneath gate electrodes (8) in the P-type base layer (3) and immediately beneath the periphery of the N-type emitter regions (4), such that the depth of the P.sup.+ layer regions immediately beneath the gate electrodes (8) is selected to be deeper than the N-type emitter regions (4).

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Tokyo, Japan

Yoshiaki Hisamoto