Kabushiki Kaisha Toshiba

Yoshiaki Hashiba

Akira Umezawa

Takuya Fujimoto

Yoshiharu Hirata

Kazushige Kanda

Toshikazu Sei

Shinji Fujii

Yukinori Uchino

Kazuhiko Kakizoe

A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor circuit forming a current mirror circuit, a resistive divider supplied with a negative voltage to be detected, and coupled to the end of the current path of the second MOS transistor circuit to generate a second voltage, a second voltage comparator circuit to compare the second voltage with a reference voltage and to generate a detection signal corresponding to the value of the negative voltage, and a detection circuit for detecting a temperature or power supply voltage, generate the control signal corresponding to the detection result, and supply the control signal to the first and second MOS transistor circuits.

Negative voltage detection circuit and semiconductor integrated circuit

A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m&#x3c;n). The second address decode circuit decodes (n&#x2212;m) bits in the row address signal. The transfer gate supplies the output of the first address decode circuit to the word line according to the output of the second address decoded circuit.

Semiconductor memory device with MOS transistors each having floating gate and control gate

A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.

Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same

A semiconductor memory device includes a memory cell array, word lines, bit lines, a control circuit, and a measurement circuit. The memory cell array has memory cells including a floating gate. The control circuit performs first control to collectively shift the threshold voltages of the memory cells to within a predetermined range with a first level as an upper limit, second control to shift a lower limit of the threshold voltages toward a second level lower than the first level, and third control to shift the lower limit to a third level. The measurement circuit measures the elapsed time from the start of the second control. The control circuit repeats the second control, and then terminates the second control when the lower limit reaches the second level or the elapsed time measured by the measurement circuit reaches the predetermined time and performing the third control.

Semiconductor memory device having memory cells with floating gates and memory cell threshold voltage control method

A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.

Growing community of inventors

Fujisawa, Japan

Yoshiaki Hashiba