Victor Company of Japan, Limited

Yoshiaki Amano

Hiroyuki Sugiyama

Koji Tanaka

Nobuaki Takahashi

Takeshi Shibamoto

Hideo Sato

Fujio Suzuki

Mitsuru Kikuchi

Seiichi Takashima

Mitsuo Kubo

Ryozo Abe

A digital video signal reproducing apparatus comprises a reproducing circuit for reproducing a digital video signal from a recording medium, which digital video signal is added with at least a write-in specifying code and a read-out specifying code for specifying a memory circuit part to picture element data groups which are obtained by subjecting a video signal to a digital pulse modulation, a detecting circuit for detecting the write-in specifying code and the read-out specifying code within a reproduced digital video signal from the reproducing circuit, a generator for generating various synchronizing signals and reference signals, first and second memory circuit parts each having a memory capacity for storing picture element data corresponding to one picture, a write controller for causing the picture element data to be written into one of the first and second memory circuit parts according to a value of the write-in specifying code, a latch circuit for latching the read-out specifying code by a vertical synchronizing signal generated from the generator, a read controller for causing stored picture element data to be successively read out from one of the first and second memory circuit parts according to a value of the read-out specifying code from the latch circuit, and a circuit for converting the picture element data read out from the first and second memory circuit parts to an analog video signal.

Digital video signal reproducing apparatus

A digital video signal reproducing apparatus comprises a reproducing circuit for reproducing a digital video signal from a recording medium, where the recording medium is time-sequentially recorded with the digital video signal having a signal format in which a header signal is added to each of divided picture element data groups which are obtained by dividing a picture element data group in terms of a predetermined unit, the picture element data group is obtained by subjecting an analog video signal to a digital pulse modulation at a sampling frequency such that a product of a number of picture element data in one scanning line and an effective number of scanning lines in one picture of a standard television system is exceedingly close to 2.sup.18 but less than 2.sup.18, and the header signal at least comprises a synchronizing signal and a picture mode identification code, a header signal reproducing circuit for discriminating the header signal within the digital video signal reproduced by the reproducing circuit and reproducing the header signal, two memory circuits into which the picture element data group within said reproduced digital video signal is written and from which a stored picture element data group is read out, a circuit for controlling write-in and read-out with respect to the two memory circuits according to a code in the reproduced header signal, and a circuit for producing an analog video signal in accordance with a standard television system from the picture element data read out from the two memory circuits.

An address signal generating circuit for a memory circuit comprises a first latch driver for producing a signal corresponding to upper m bits of a 2m-bit address signal which is to be generated, where m is an integer, a second latch driver for producing a signal corresponding to lower m bits of the 2m-bit address signal, a circuit for dividing a 2m-bit signal which has a predetermined value into upper m bits and lower m bits and for alternately producing signals corresponding to the upper and lower m bits, a first adder for adding the value of n bits in the signal which has the predetermined value and the value of upper n bits in an output signal of the first or second latch driver and for producing an n-bit signal, where n is an integer less than m, a second adder for adding the value of m-n bits in the signal which has the predetermined value and lower m-n bits of the output signal of the first or second latch driver and for producing an (m-n)-bit signal, an adding circuit for supplying a carry signal of the first or second adder to the second or the first adder so as to add the carry signal with another input signal of the second or the first adder, and a driver control circuit for controlling the first and second latch drivers to alternately and time-divisionally produce upper m bits of the 2m-bit address signal and lower m bits of the 2m-bit address signal by alternately latching an m-bit output signal of the first and second adders in the first and second latch drivers.

Address signal generating circuit for a memory circuit

A digital video signal recording system and reproducing apparatus comprise a circuit for independently subjecting a luminance signal and two kinds of color difference signals of a color picture information to digital pulse modulation, to produce a digital luminance signal and two kinds of digital color difference signals, a circuit for dividing the digital luminance signal and the two kinds of digital color difference signals into picture element data groups, in terms of specific number of rows or columns which are adjacent on a screen, and adding a header signal at least comprising a synchronizing signal, a picture mode identification code, and a picture information quantity identification code to a beginning position of each of the divided picture element data groups comprising the digital luminance signal and the two kinds of digital color difference signals, to produce a digital video signal having a signal format in which the digital luminance, the two kinds of digital color difference signals, and the header signal are time-sequentially multiplexed, a circuit for recording the digital video signal onto a recording medium, a circuit for writing each of the divided picture element data groups picked up and reproduced from the recording medium into a memory circuit according to codes within the header signal, and a circuit for producing an analog video signal in accordance with a standard television system from picture element data read out from the memory circuit.

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Fujisawa, Japan

Yoshiaki Amano