Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Yoshiaki Aizawa

Mitsuhiko Kitagawa

Yoichiro Kurita

Masayuki Sugiura

Takanobu Kamakura

Hisaya Okumura

Toshimitu Katoh

Takashi Nishimura

Toshimitsu Kato

Masaru Yumura

Ryujiro Saso

Masayuki Sonoda

An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.

Electronic device

The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layerand a n-type source layerselectively formed on the surface of the p-type base layer. A n-type drain layeris formed in a position apart from the p-type base layer. On the surface of the region between the p-type base layerand the n-type drain layer, a n-type drift semiconductor layerand a p-type drift semiconductor layerare alternately arranged from the p-type base layerto the n-type drain layer. Further, in the region between the n-type source layerand the n-type drain layer, a gate electrodeis formed via a gate insulating film. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layerand the p-type drift semiconductor layeror by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.

Field effect transistor and application device thereof

A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage.

Micro electro mechanical system apparatus

The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layerand a n-type source layerselectively formed on the surface of the p-type base layer.. A n-type drain layeris formed in a position apart from the p-type base layer. On the surface of the region between the p-type base layerand the n-type drain layer, a n-type drift semiconductor layerand a p-type drift semiconductor layerare alternately arranged from the p-type base layerto the n-type drain layer. Further, in the region between the n-type source layerand the n-type drain layer, a gate electrodeis formed via a gate insulating film. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layerand the p-type drift semiconductor layeror by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are atpotential.

A field-effect transistor includes a silicon layer formed on an insulating film, a first-conductivity-type base and a second-conductivity-type source layers formed in the silicon layer being adjacent to each other, a second-conductivity-type drain layer formed in the silicon layer being separated from the source layer with the base layer being interposed therebetween, a gate-to-drain offset layer formed between the base and drain layers, having a resistance higher than that of the base layer, and a gate electrode formed on at least a surface of the base layer via a gate insulating film wherein the silicon layer in which the base layer is formed is a strained silicon layer.

Field-effect transistor, semiconductor device, and photo relay

A drive circuit and relay circuit using this drive circuit are provided, the drive circuit including: a first terminal connected to a drive electrode located at one side of a mechanical switch contact driven by static electricity; a second terminal connected to a drive electrode located at the other side of the switch contact; a photoelectromotive force element connected to the first terminal and the second terminal, optically coupled to a light emitting element, and including at least two photodiode arrays which are serially connected; and an electronic inductor circuit (bypass circuit) connected in parallel with at least one of the photodiode arrays in the photoelectromotive force element.

Drive circuit of switch and relay circuit

An optical semiconductor relay comprises a light emitting element converting an electrical signal into an optical signal, a first photodiode array receiving the optical signal from the light emitting element. The first photodiode array converts the optical signal into an electrical signal. The relay is further provided with a first diode having one electrode connected to one end of the first photodiode array and a MOSFET. The MOSFET has a gate terminal connected to other electrode of the first diode, and a source terminal connected to other end of the first photodiode array. A second photodiode array is arranged to receive the optical signal from the light emitting element. The second photodiode array converts the optical signal into an electrical signal and has both ends connected to the respective electrodes of the first diode. A control circuit connected between the gate and source terminals of the MOSFET.

Optical semiconductor relay

The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer and a n-type source layer selectively formed on the surface of the p-type base layer . A n-type drain layer is formed in a position apart from the p-type base layer . On the surface of the region between the p-type base layer and the n-type drain layer , a n-type drift semiconductor layer and a p-type drift semiconductor layer are alternately arranged from the p-type base layer to the n-type drain layer . Further, in the region between the n-type source layer and the n-type drain layer , a gate electrode is formed via a gate insulating film . With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layer and the p-type drift semiconductor layer or by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.

In a semiconductor integrated circuit consisting of a plurality of semiconductor chips each having a plurality of islands, two or more bonding wires each having different potential are connected to bonding pads formed on the surface of semiconductor chips. The islands are isolated by a dielectric isolation region comprising polysilicon film and isolation film formed in an isolation groove. The polysilicon film is exposed at a dicing line region around the semiconductor chip and a surface of the polysilicon film is made highly resistive. If two or more bonding wires come into contact with the polysilicon film exposed at a peripheral region of the semiconductor chip to cause short circuit, parasitic conductance does not occur between two or more bonding wires because the peripheral region of the semiconductor chip has high resistivity, whereby variation in characteristics of the semiconductor integrated circuit can be suppressed.

Dielectrically-isolated integrated circuit

A bidirectional semiconductor switch employs two insulated gate semiconductor devices such as insulated gate bipolar transistors (IGBTs) that are connected oppositely in parallel, with the collector of one of the IGBTs being connected to the emitter of the other. The gates of the IGBTs are biased by gate controllers that are potentially independent of each other. The semiconductor switch is capable of controlling a direct current as well as an alternating current at a low ON-state voltage, reducing a conduction loss, and improving efficiency.

Bidirectional semiconductor switch

A semiconductor relay has two output MOSFET pairs, each of which is series-connected with the other. Each MOSFET pair is comprised of two MOSFETs series-connected oppositely to each other, and these MOSFETs are controlled to turn on or off simultaneously. The semiconductor relay further includes a switch, which is inserted between the ground and the junction of the two MOSFET pairs. When these MOSFETs are in an off condition, said switch is closed in order to release electric charges accumulated on said MOSFETs and to increase the off-resistance of this semiconductor relay. On the other hand, when the MOSFETs are in an on condition, said switch is opened so as to connect both MOSFET pairs in series. As a result, a semiconductor relay having a high off-resistance can be obtained without increasing the on-resistance.

Growing community of inventors

Kanagawa-ken, Japan

Yoshiaki Aizawa