Marvell Israel (misl) Ltd.

Marvell Semiconductor Israel Ltd.

Galileo Technology Ltd.

Yosef Solt

Eitan Joshua

Sorel Horovitz

Reshef Bar Yoel

Yosef Haviv

Michael Levi

David Shemla

Ofir Keren

Eitan Medina

Aron Wohlgemuth

Amit Avivi

Ofer Benjamin

Eli Kurin

Michael Moshe

Eyal Waldman

Doron Shefert

Asaf Idan

Aspects of the disclosure include an integrated circuit (IC) that includes a first input port configured to receive a test pattern, a second input port configured to receive a signature pattern, a set of interconnected circuit elements, and a comparison circuit. The signature pattern is indicative of an expected test output pattern in response to the test pattern. The set of interconnected circuit elements is configured to generate a test output pattern in response to the test pattern being passed through the set of interconnected circuit elements. The comparison circuit is configured to compare the test output pattern to the signature pattern, generate a test result based on a comparison result of the test output pattern to the signature pattern, and output the test result to the test apparatus.

Integrated circuit package receiving test pattern and corresponding signature pattern

Systems and methods are provided for an integrated circuit system. A plurality of separate integrated circuit dies are coupled together to form an integrated circuit package, a first integrated circuit die including an input and a last integrated circuit die including an output, ones of the plurality of integrated circuit dies including a testing circuit associated with a corresponding integrated circuit die. The testing circuit includes a testing path for testing functionality of the corresponding integrated circuit die, a bypass path bypassing the testing path, and control circuitry for selecting between an output of the testing path and an output of the bypass path, the control circuitry being configured to select the output of the testing path or the output of the bypass path and to pass the selected output to a subsequent integrated circuit die among the plurality of coupled circuit dies.

Systems and methods for automatic test pattern generation for integrated circuit technologies

Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes functional circuits configured to perform desired functions when a chip temperature is higher than a threshold, such as a room temperature. The IC chip includes a warm-up module configured to warm-up the IC chip in a warm-up mode to raise the chip temperature above the threshold. A method for warming up an IC chip prior to operation is also disclosed.

Method and apparatus for warming up integrated circuits

Aspects of the disclosure provide a method for testing. The method includes determining an electrical characteristic of an integrated circuit (IC), subjecting the IC to a stress test, characterizing the electrical characteristic of the IC subsequently to subjecting the IC to the stress test, and determining a quality attribute of the IC based on a comparison of the respective electrical characteristics of the IC before and after subjecting the IC to the stress test.

Method and apparatus for testing

Packets are received via a plurality of ports, and packets are switched between the plurality of ports. Packets received via the plurality of ports are stored in a memory, and buffers are allocated in the memory for storing packets. An aging mechanism to indicate allocated buffers that are to be deallocated is implemented, and buffers that are indicated to be deallocated by the aging mechanism are deallocated.

Buffer management architecture

A memory system includes an array of memory cells and a repair module. Multiple memory cells in the array are redundant to other memory cells in the array. The repair module iteratively tests the array. During the iterative testing of the array, the repair module, during each test of the array, (i) identifies one or more defective memory cells in the array, if any, and (ii) in response to one or more defective memory cells being identified during the test, respectively replaces the one or more defective memory cells with one or more memory cells that are redundant to other memory cells in the array. The repair module performs the iterative testing of the array until (i) the repair module does not detect a defective memory cell or (ii) no memory cells of the memory cells that are redundant remain available for replacement of a defective memory cell.

Method and system for iteratively testing and repairing an array of memory cells

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.

Method and apparatus for memory test

A memory system includes an array of memory cells. The array of memory cells includes redundant memory cells. The redundant memory cells include at least two of a redundant row and a redundant column of memory cells. The repair module is configured to (i) identify at least two of a row and a column of the array of memory cells having non-operational memory cells and (ii) substitute the at least two of the row and the column of the array of memory cells with selected rows or columns of the redundant memory cells based on X predetermined sequences of substitutions. The repair module is configured to detect a failure in the array of memory cells that cannot be repaired using the X predetermined sequences of substitutions, and use an alternative repair sequence to repair the non-operational memory cells based on the detection of the failure.

Memory repair system and method

Aspects of the disclosure provide an integrated circuit that is configured for parallel memory testing. The integrated circuit includes a first memory block and a first scrambler coupled to the first memory block during a memory testing. The first memory block includes a first memory array, and a first envelope configured to translate a driving address of the first memory block into a corresponding physical address of the first memory array based on a first memory configuration for using the first memory array. The first scrambler is configured to provide a first plurality of driving addresses and associated first data to the first envelope based on the first memory configuration. The first plurality of driving addresses and the first data are used to test the first memory array according to a first test pattern. Further, the integrated circuit includes a second memory block and a second scrambler coupled to the second memory block during the memory testing. The second memory block includes a second memory array, and a second envelope configured to translate a driving address into a physical address of the second memory array based on a second memory configuration for using the second memory array. The second scrambler is configured to provide a second plurality of driving addresses and associated second data to the second envelope based on the second memory configuration. The second plurality of driving addresses and the second data are used to test the second memory array according to a second test pattern.

Systems and apparatus for managing buffers in a buffer memory are described. In at least one aspect, a system includes a buffer memory including a plurality of buffers; an allocation memory including a plurality of allocation data elements associated with the plurality of buffers; an allocation clear register coupled with the allocation memory; a reclaim memory including a plurality of reclaim data elements each associated with an allocation data element and corresponding buffer; a reclaim clear register coupled with the reclaim memory; an allocation register configured to receive one or more allocation data elements from the allocation memory; and a buffer manager.

A data processing system includes a memory configured to store data in a plurality of addressable storage spaces thereof, wherein the memory includes a first data port and a second data port, a first functional block configured to access the memory via the first data port to perform a logic operation, and a second functional block configured to access the memory via the second data port to perform soft error scrubbing in the data stored in the memory.

System and method for soft error scrubbing

An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test pattern and output the first output test pattern, a switching unit for selecting and outputting one of the input test pattern and the first output test pattern as a selected test pattern, and the second scan chain portion for testing the second logic circuit based on the selected test pattern from the switching unit and output the second output test pattern. The switching unit selects one of the input test pattern and the first output test pattern based on at least one of a logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the logic circuits.

Integrated circuit testing using segmented scan chains

A system includes a first circuit generating error-correction (EC) bits based on test data. Memory comprises a plurality of memory lines each including a data portion storing the test data and an error-correction (EC) portion storing corresponding ones of the EC bits. An input receives the test data. A switching device selectively outputs one of the test data from the input and the EC bits and the test data from the first circuit to the memory. The test data comprise T pairs of test vectors. A first test vector of each of the T pairs of test vectors is an inverse of a second test vector of each of the T pairs of test vectors. Each of the first test vectors in the T pairs of test vectors is unique and each of the second test vectors in the T pairs of test vectors is unique. T is an integer greater than one.

Error-correction memory architecture for testing production errors

A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory by substituting the selected memory elements with the redundant memory elements. A second repair sub-circuit hard repairs the memory based on the substitutions.

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Misgav, Israel

Yosef Solt