Toshiba Memory Corporation

Kioxia Corporation

Toshiba Memory Cororation

Yorinobu Fujino

Kosuke Hatsuda

Yoshiaki Osada

Katsuhiko Hoya

Jieyun Zhou

According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.

Memory device

According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period.

Resistance change memory device and associated methods

A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.

Semiconductor storage device

According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.

According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.

According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.

According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.

Growing community of inventors

Hachioji Tokyo, Japan

Yorinobu Fujino