Intel Corporation

Yorgos Palaskas

Ashoke Ravi

Telesphor Kamgaing

Valluri Ramana Rao

Dinesh Somasekhar

Ofir Degani

Stefano Pellerano

Krishnamurthy Soumyanath

Hasnain Lakdawala

Masoud Sajadieh

Richard B Nicholls

Mostafa Elmala

Itshak Hod

An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Chip packages including through-silicon via dice with vertically inegrated phased-array antennas and low-frequency and power delivery substrates

Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.

Subranging for a pulse position and pulse width modulation based transmitter

A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.

Phase noise minimized phase/frequency-locked voltage-controlled oscillator circuit

Architectures including digital outphasing transmitters. Digital signal generation circuitry generates at least two base-band sinusoid signals. Bandpass modulation circuitry is coupled to receive the base-band sinusoid signals and generates at least two modulated digital signals. Power amplifiers are coupled to receive the modulated digital signals to amplify the modulated digital signals. The amplified modulated signals are combined and transmitted.

Digital outphasing transmitter architecture

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Portland, OR, United States of America

Yorgos Palaskas