Motorola Corporation

Freescale Semiconductor,inc.

Wintegra Ltd.

Yoram Yeivin

Eliezer Weitz

Moti Kurnick

Avi Hagai

Avi Shalev

Adi Katz

Udi Barel

Yehuda Shaik

Eran Kirzner

Yehuda Rudin

Boaz Shachar

Ido Reuveny

Ricardo Berger

Ronen Weiss

Yossi Socoletzki

Micha Stern

Ronen Amrani

Nahum Rozen

Eli Wietz

In some embodiments of the present invention, applications presenting user information streams at a service access point (SAP) to AAL-2 above the Common Part Sublayer (CPS) may provide values for predefined parameters that may determine how frames of information in the user information streams are segmented in run-time into CPS packets and packed into CPS protocol data units (CPS-PDU), each of which forms the payload of an ATM cell. These parameter values may be defined per channel identifier (CID) or for a group of CIDs.

Method and apparatus for dynamic bandwidth allocation for voice and data multiplexing over AAL-2 connections

A communication controller ( ) for handling and processing data packets received from a large number of communication channels ( ). The communication controller ( ) comprising of: a processor ( ) for processing data; a serial interface ( ), coupled to the communication channels ( ). A multi channel controller ( &prime;) coupled to the serial interface ( ) and the processor ( ), for interfacing between the communication channels ( ) and the processor ( ). The communication channels ( ) and the serial interface ( ) send and receive data packets. The processor ( ) sends, receives and processes data words. The multi channel controller ( ) receives data packets from the serial interface ( ), concatenates data packets and sends data words to the processor ( ). The multi channel controller ( ) receives data words from the processor ( ), and transmits data packets to the serial interface ( ).

Multi channel controller

A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.

High performance communication controller for processing high speed data streams wherein execution of a task can be skipped if it involves fetching information from external memory bank

A communication system (100) comprises a processor (150), a channel memory (160), a communication line (180), a transmit connect table (146), a transmit scheduler table (144), and a program memory (148). The channel memory (160) stores channels (161) with data cells (102). The processor (150) writes channel identifiers (e.g., 1 2) into schedule fields (110-V) of the transmit scheduler table (144) and points with a pointer R and a pointer V to the schedule fields (110-V). The pointers R and V identify fields in which the processor (150) looks up for a first channel identifier. The processor (150) forwards data cells (102) from the channel memory (160) to the communication line (180) for the channel (161) corresponding to the first channel identifiers. Then, the processor (150) moves the first channel identifier to an other field and writes a second channel identifier stored in the transmit connect table (146) to the field of the first channel identifier.

Apparatus and method for transmitting data

A data communication system (2) provides a circuit and method for prioritizing and controlling the transfer of data to and from a plurality of communication channels (6-11). The data communication system defines a predetermined data threshold level (X,Y) for a data buffer (16-21) for each of the plurality of communication channels. A service request signal is generated for a one of the plurality of communication channels when a respective data buffer stores data to be transferred. The data communication system generates a threshold signal for a communication channel when a data value stored in a respective data buffer reaches a predetermined data threshold level of the data buffer. The priority levels of the communication channels which generate threshold and service request signals are then compared to determine a high priority communication channel. The highest priority communication channel is then serviced.

Data communication system for controlling prioritization and transfer of

In a clock generator (100), an oscillator (30) supplies an oscillator signal (38) to a first trigger (10) and to a second trigger (20). The triggers change the oscillator signal (38) to a first and a second trigger signal (18, 28). The second trigger (20) has a larger hysteresis range than the first trigger (10), so that the first trigger signal (18) starts toggling before the second trigger signal (28) starts toggling. A detector (40) determines that the second trigger signal (28) toggles at least three times, that means that the oscillator signal (38) goes over the larger hysteresis range in two directions. The detector (40) provides a result to a control circuit (50) which derives a clock signal (98) from the first trigger signal (18).

Clock generator and method for generating a clock signal

Transparent Time Division Multiplexer (TDM) Superchannels including multiple time slots assigned to a single logical channel are synchronized between transmitter and receiver. For a given time slot in an idle logical channel (286), the transmitter only starts transmitting output if this is the first time slot assigned to the logical channel (288) and output is available for the logical channel (290). Starting to transmit output is postponed (289) if this is not the first time slot assigned to the logical channel. Correspondingly, the receiver only expects new data blocks to start in the first time slot assigned to the logical channel.

Synchronization of transparent TDM superchannels

A time slot assigner (20) for a serial communication system utilizes an encoded field of data. The time slot assigner (20) has a memory (52) for storing encoded data, a digital counter (60), a prescaler (62), a dedicated latch (58), and a time slot control logic (56). The enclosed data is partitioned into encoded data fields within the memory. A first encoded data field is utilized to indicate a last (LST) encoded data entry of a plurality of entries in the memory to be processed collectively, a second encoded data field (BRS) indicates a bit resolution of the data, a third encoded data field contains a count (CNT) value, and a fourth encoded data field selects a serial communication channel (CSEL). The time slot assigner (20) is activated by an active strobe start cycle signal, and is deactivated in response to a predetermined activated encoded data field.

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Hod Hasharon, Israel

Yoram Yeivin