Cypress Semiconductor Corporation

Saifun Semiconductors Ltd.

Infineon Technologies LLC

Spansion Israel Ltd

Spansion Llc.

Yoram Betser

Shivananda Shetty

Alexander Kushnarenko

Chun Chen

Eduardo Maayan

Pawan Kishore Singh

Kobi Danon

Oleg Dadashev

Yair Sofer

Amichai Givant

Kuo Tung Chang

Amir Rochman

Tio Wei Neo

Giovanni Mazzeo

Shenqing Fang

Kuo-Tung Chang

Joseph Shor

Stefano Amato

Avri Harush

Stephan Rosner

Cliff Zitlaw

Roni Varkony

Alex Kushnarenko

Yaal Horesh

James Minsu Pak

Oren Shlomo

Cindy Sun

Ori Elyada

Idan Koren

Jonas Neo

Pawan Singh

Uri Kotlicki

Arieh Feldman

Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Dynamic sensing levels for nonvolatile memory devices

In an embodiment, a memory circuit includes: a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits and is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on a selection input of the data multiplexer. The data path is configured to cause a propagation of data from a data output of the data multiplexer to a data input of the logic circuit.

Data path circuit and method

A method of operating a memory device includes: supplying one or more supply voltages to a memory array; and monitoring the one or more supply voltages, which includes: selecting, from the one or more supply voltages, a selected supply voltage; converting, using an analog-to-digital converter (ADC), an internal reference voltage of the memory device and a scaled version of the selected supply voltage into one or more digital values; generating a calibrated measurement result using the one or more digital values; and determining whether the calibrated measurement result is within a pre-determined range.

Analog signals monitoring for functional safety

A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Erase power loss indicator (EPLI) implementation in flash memory device

A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.

Multi-ported nonvolatile memory device with bank allocation and related systems and methods

Embodiments of the present disclosure provide systems and methods of reducing the EMI effect generated by such analog blocks. By varying the clock frequency in time of oscillators used by such analog blocks, the EMI energy may be spread over a wide spectrum range thereby reducing the peak energy for the main frequency. To achieve this, the oscillator frequency is directly varied using analog mechanisms. The mechanisms may be based on a synchronized method for increasing/decreasing the current that is charging/discharging the oscillator capacitor. The frequency variation may be achieved by analog control of the extra charge/discharge current.

Method and circuit for electromagnetic interference (EMI) reduction of analog blocks

Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Suppression of program disturb with bit line and select gate voltage regulation

A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

Non-volatile memory device and method of blank check

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Non-volatile memory array with memory gate line and source line scrambling

Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.

Methods, circuits, devices and systems for comparing signals

Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.

Methods, circuits, devices, and systems for sensing an NVM cell

Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

Growing community of inventors

Mazkeret Batya, Israel

Yoram Betser