Samsung Electronics Co., Ltd.

Yoonyoung Jung

Juhun Park

Deokhan Bae

Yuri Lee

Sooyeon Hong

Sungmin Kim

Myungyoon Um

Inyeal Lee

Jin-Wook Kim

An integrated circuit device includes: a first fin-type active region and a second fin-type active region that extend on a substrate in a straight line in a first horizontal direction and are adjacent to each other in the first horizontal direction; a fin isolation region arranged between the first fin-type active region and the second fin-type active region on the substrate and including a fin isolation insulation structure extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of gate lines extending on the first fin-type active region in the second horizontal direction, wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined to be closer to a center of the fin isolation region in the first horizontal direction from a lowermost surface to an uppermost surface of the first gate line.

Integrated circuit device having inclined structures

Integrated circuit devices may include a fin-type active region, a gate line extending on the fin-type active region, a source/drain region on the fin-type active region and adjacent to the gate line, an interlayer insulating film covering the source/drain region, a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region, a metal plug in the source/drain contact hole, and a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole. The metal plug includes a lateral expansion portion and a through portion vertically extending from the lateral expansion portion toward the source/drain region. A width of the lateral expansion is greater than a width of the through portion, and a topmost surface of the conductive barrier film is closer than a topmost surface of the metal plug to the substrate.

Integrated circuit devices and methods of manufacturing the same

A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

Semiconductor memory devices and methods of fabricating the same

A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

Semiconductor device

Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.

Semiconductor device and method of fabricating the same

A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.

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Suwon-si, South Korea

Yoonyoung Jung