Samsung Electronics Co., Ltd.

Yoonyoung Choi

Junyoung Lee

Sanghoon Song

Youn-Gun Jung

Munhee Jang

Youngjun Cho

Kiseok Lee

Jiyoung Ahn

Seungjin Kim

Jiseok Hong

Seunguk Han

Seoryong Park

Sangho Lee

Byunghyun Lee

Yongseok Ahn

Sangjae Park

Jinwoo Bae

Joonkyu Rhee

Byeongjoo Ku

Hyunyong Kim

Minsub Um

Hangeol Lee

Sungsoo Yim

Sunghwan Kim

Sejin Park

Tae-Kyu Kim

Eunjung Kim

Myeong-Dong Lee

Junhyeok Ahn

Jay-Bok Choi

Hyukwoo Kwon

Yongjun Cho

Hyo-Sub Kim

Byung-Hyun Lee

Jamin Koo

Ju Hyung We

Hyun-Sil Hong

Heesook Cheon

Dongkyun Lee

Taehee Han

Bo-Wo Choi

Suklae Kim

Bowo Choi

Hyunsil Hong

Byeongmoo Kang

Seongmo Koo

A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

Semiconductor memory device and method of fabricating the same

An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

Integrated circuit device

A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.

Semiconductor memory device

An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

Integrated circuit device having a bit line and a main insulating spacer with an extended portion

A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

Semiconductor devices

An integrated circuit device including a lower electrode on a substrate, the lower electrode including a first lower electrode portion extending in a first direction perpendicular to a top surface of the substrate and including a first main region and a first top region, and a second lower electrode portion extending in the first direction on the first lower electrode portion and including a second main region and a second top region; a first top supporting pattern surrounding at least a portion of a side wall of the first top region of the first lower electrode portion; and a second top supporting pattern surrounding at least a portion of a side wall of the second top region of the second lower electrode portion, and the second lower electrode portion includes a protrusion protruding outward to the second top supporting pattern.

Integrated circuit device and method of manufacturing the same

An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.

Integrated circuit semiconductor device

A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

Methods of fabricating capacitor and semiconductor device and semiconductor devices and apparatus including the same

A semiconductor device includes a transistor on a semiconductor substrate including a first area and a second area, and having a gate structure and an impurity area, a first interlayer insulating film covering the transistor, and having a contact plug electrically connected to the impurity area, a capacitor including a lower electrode on the first interlayer insulating film in the second area and electrically connected to the contact plug, a dielectric film coating a surface of the lower electrode, and an upper electrode on the dielectric film, and a support layer in contact with an upper side surface of the lower electrode to support the lower electrode, and extending to the first area, in which the support layer has a step between the first area and the second area.

Methods of forming a capacitor, semiconductor device, and fine pattern, and semiconductor device formed by the methods

A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.

Method of fabricating a semiconductor device

A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.

Semiconductor device including storage node electrode having filler and method for manufacturing the same

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Yoonyoung Choi