Samsung Electronics Co., Ltd.

University of California

Yoontae Hwang

Wandon Kim

Geunwoo Kim

Heonbok Lee

Taegon Kim

Hanki Lee

Hyunbae Lee

Shadi A Dayeh

Renjie Chen

Atsunori Tanaka

Ren Liu

Yun Goo Ro

Sang Heon Lee

An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

Integrated circuit device

A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

Method of manufacturing a semiconductor device

A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

Semiconductor device

A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.

Addressable vertical nanowire probe arrays and fabrication methods

Growing community of inventors

Seoul, South Korea

Yoontae Hwang