Samsung Electronics Co., Ltd.

Sungkyunkwan University

Yoonmyung Lee

Chisung Bae

Jung-Hoon Chun

Hyungmin Gi

Sang Joon Kim

Jaehong Jung

Jongmin Lee

Junyoung Park

Seungchul Jung

Sangjoon Kim

Jaemin Choi

Donghyeon Lee

Jonghan Kim

Jung Hoon Chun

Yeohoon Yoon

Ji Ho Song

Changyoun Im

Jiho Song

Jua Lee

Ju A Lee

Yongmin Lee

A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.

Scan flip-flop, scan chain circuit including the same, and control method of the scan flip-flop

A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.

Neural network based method and device

A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.

Device with neural network

An apparatus and method for tracking maximum power are disclosed. The apparatus is configured to track a maximum power at a certain node of an electronic circuit, adjust an impedance of the electronic circuit such that power at the node is maximal, and adjust an impedance of the electronic circuit by comparing power at two points in time to increase power. The apparatus for tracking a maximum power, includes a charge sharing capacitor connected to an initial capacitor in parallel, a first switch disposed between the initial capacitor and an energy harvesting power supply, a second switch disposed between the initial capacitor and the charge sharing capacitor, a third switch disposed between the energy harvesting power supply and a comparator, and a switched-capacitor power converting circuit configured to control the initial capacitor.

Apparatus and method for tracking maximum power

A method for physically unclonable function (PUF) cell-pair remapping includes combining PUF cell-pairs between PUF cells in a first array and PUF cells in a second array, acquiring physical parameters for each of the PUF cell-pairs, selecting PUF cell-pairs based on a comparison of the acquired parameters with a first reference, and remapping the selected PUF cell-pairs.

Method and apparatus with physically unclonable function (PUF) cell remapping and PUF circuit

A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.

Boost converter and boost converter cell

An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.

Low power RC oscillator with switched bias current

An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.

Growing community of inventors

Seongnam-si, South Korea

Yoonmyung Lee