Samsung Electronics Co., Ltd.

Yoonjong Song

Gwanhyeob Koh

Kilho Lee

Shinhee Han

Jung Hyuk Lee

Kiseok Suh

Daeeun Jeong

Myoungsu Son

Gwan-Hyeob Koh

Yongkyu Lee

Seung Pil Ko

Yong-Seok Chung

Yongjae Kim

Yong Kwan Kim

Kyungtae Nam

Boyoung Seo

Byoungjae Bae

Seulji Song

Kangho Lee

Junghyuk Lee

Hyunsung Jung

Hyemin Shin

Doyoun Park

A self-selecting memory device includes a first conductive line on a substrate, a first memory cell on the first conductive line, a second conductive line on the first memory cell, a second memory cell on the second conductive line, and a third conductive line on the second memory cell. The first memory cell includes a first electrode, a first switching memory unit and a second electrode sequentially and vertically stacked. The second memory cell includes a third electrode, a second switching memory unit and a fourth electrode sequentially and vertically stacked. The first switching memory unit includes a first SSM pattern contacting an upper surface of the first electrode and including an OTS material, and a first nitrogen-containing pattern contacting an upper surface of the first SSM pattern and a lower surface of the second electrode and including an OTS material doped with nitrogen.

Self-selecting memory devices

A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

Magnetic memory device

A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Semiconductor devices

A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.

Magnetic memory device and method for manufacturing the same

Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.

Magnetic memory devices

Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

Memory device and programming method

Disclosed are a magnetic memory device and a method of fabricating the same. The magnetic memory device comprises a bottom electrode on a substrate, a magnetic tunnel junction pattern including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer that are sequentially stacked on the bottom electrode, and a top electrode on the magnetic tunnel junction pattern. The bottom electrode comprises a first bottom electrode and a second bottom electrode on the first bottom electrode. Each of the first and second bottom electrodes comprises metal nitride. The first bottom electrode has a crystallinity higher than that of the second bottom electrode.

Magnetic memory device and method of fabricating the same

A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

Semiconductor device

The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.

Method for forming a hard mask pattern and method for manufacturing a semiconductor device using the same

Disclosed is a method for manufacturing a magnetic memory device. The method for manufacturing a magnetic memory device comprises sequentially forming a first magnetic layer, a tunnel barrier layer, and a second magnetic layer on a substrate, forming a boron absorption layer on the second magnetic layer, sequentially forming a metal capping layer and an oxygen donor layer on the boron absorption layer, and performing a heat treatment process to diffuse at least a portion of oxygen atoms included in the oxygen donor layer into the metal capping layer and the boron absorption layer. The metal capping layer has a greater oxygen diffusivity than the oxygen donor layer.

Methods for manufacturing magnetic memory devices

A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other. An isolation pattern is on the active region and the isolation region. The isolation pattern is between the first and second cell interconnection structures. Contact structures are between the first and second cell interconnection structures. The contact structures are at both sides of the isolation pattern and overlap the active region. Insulating patterns are between the first and second cell interconnection structures. The insulating patterns are at both sides of the isolation pattern and overlap the isolation region. Common source regions are under the first and second cell interconnection structures. The common source regions are in the active region. An isolating gate pattern that has a line shape is under the isolation pattern.

Semiconductor device and method of forming the same

Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.

A magnetic memory device and a method for manufacturing the magnetic memory device are disclosed. The method includes forming a first interlayer insulating layer on a substrate, forming a first conductive pattern that penetrates the first interlayer insulating layer, forming a mold insulating layer that includes first and second mold insulating layers on the first interlayer insulating layer, forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer, and forming a magnetic tunnel junction pattern on the second conductive pattern. The first mold insulating layer is in contact with the first conductive pattern, and the second mold insulating layer is disposed on the first mold insulating layer.

Growing community of inventors

Seoul, South Korea

Yoonjong Song