Imagination Technologies Limited

Apple Inc.

Yoong Chert Foo

Jonathan Mark Redshaw

Terence M Potter

John William Howson

Kenneth C Rovers

Benjiman L Goodman

Andrew Davy

Salil Sahasrabudhe

Justin A Hensley

Frank W Liljeros

Karl D Mann

Ralph Clay Taylor

Jonathan M Redshaw

Winnie W Yeung

Morrie Berglas

Jeffrey T Brady

Christopher A Burns

Ali Rabbani Rankouhi

William V Miller

Sergio V Tota

Cheng Li

Zelin Zhang

Aroun Demeure

Anjana Rajendran

Max J Batley

Adam J Smith

Donald R Desota

Christopher G Martin

Sheenam Jayaswal

David K Li

A decoder decodes a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format. A parameter decode unit decodes configuration data for the received block of texture data, a colour decode unit decodes colour endpoint data for the plurality of texels in dependence on the configuration data, a weight decode unit decodes interpolation weight data for each of the plurality of texels in dependence on the configuration data, and at least one interpolator unit calculates a colour value for each of the plurality of texels using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data. At least one of the parameter decode unit, colour decode unit and weight decode unit decodes intermediate data from the received block that is common to the decoding of a subset of texels of that block and uses that decoded data as part of the decoding of at least two of the plurality of texels.

Multi-output decoder for texture decompression

Techniques are disclosed relating to storage techniques for fragment data. In some embodiments, one or more storage circuits are configured to store sample color data for processing by shader processors including a data structure that includes first and second elements configured to store color data for first and second colors, respectively. In some embodiments, control circuitry is configured to generate color state metadata to map samples in a region of pixels to colors in elements of the data structure, including to map multiple samples to the first element of the data structure. In some embodiments, control circuitry is configured to access the color state metadata to determine a mapped element of the data structure for a given sample and read the color data from the mapped element of the data structure. Disclosed techniques may improve, reduce or avoid duplication and thereby improve cache efficiency for accesses to color data.

Color state techniques for graphics processors

Techniques are disclosed relating to conversion operations in the context of integer and floating-point processor operations. In some embodiments, floating-point pipeline circuitry is configured to execute a single instruction to convert an N-bit integer value to an M-bit floating-point result. To execute the instruction, source modifier circuitry may generate an intermediate M-bit representation based on the N-bit integer value. Fused multiply-add circuitry may perform a fused multiply-add operation to generate the M-bit floating-point result, where the fused multiply-add operation operates on: the intermediate M-bit representation, a quantization scale factor value indicated by the instruction, and a zero-point value indicated by the instruction. In some embodiments that support down-conversion, the floating-point pipeline circuitry is also configured to execute a single instruction to convert an M-bit floating-point value to an N-bit integer result value.

Hardware support for conversion between integer and floating-point data

Techniques are disclosed relating to thread preemption in the context of memory-backed registers. In some embodiments, a memory hierarchy includes one or more cache levels and one or more memory circuits. Execution circuitry may operate on operands in architectural registers to execute instructions of threads, where data for the architectural registers is stored and backed by the memory hierarchy. Control circuitry may, in response to a context switch indication for a given thread: flush and invalidate a set of architectural register data from a first cache level and store memory page information (e.g., a page catalog base address) associated with the set of architectural register data.

Preemption techniques for memory-backed registers

Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

On-demand memory allocation

Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.

Multi-stage thread scheduling

Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

Cache control to preserve register data

A method and system for generating two or three dimensional computer graphics images using multisample antialiasing (MSAA) is provided, which enables memory bandwidth to be conserved. For each of one or more pixels it is determined whether all of a plurality of sample areas of that pixel are located within a particular primitive. For those pixels where it is determined that all the sample areas of that pixel are located within that primitive, a value is stored in a multisample memory for a smaller number of the sample areas of that pixel than the total number of the sample areas of that pixel and data is stored indicating that all the sample areas of that pixel are located within that primitive.

Method and system for multisample antialiasing

A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.

Task execution in a SIMD processing unit with parallel groups of processing lanes

Techniques are disclosed relating to cache footprint management. In some embodiments, execution circuitry is configured to perform operations for instructions from multiple threads in parallel. Cache circuitry may store information operated on by threads executed by the execution circuitry. Scheduling circuitry may arbitrate among threads to schedule threads for execution by the execution circuitry. Tracking circuitry may determine one or more performance metrics for the cache circuitry. Control circuitry may, based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads considered for arbitration by the scheduling circuitry, to control a footprint of information stored by the cache circuitry. Disclosed techniques may advantageously reduce or avoid cache thrashing for certain processor workloads.

Cache footprint management

A SIMD microprocessor is configured to execute programs divided into discrete phases. A scheduler is provided for scheduling instructions. A plurality of resources are for executing instructions issued by the scheduler, wherein the scheduler is configured to schedule each phase of the program only after receiving an indication that execution of the preceding phase of the program has been completed. By splitting programs into multiple phases and providing a scheduler that is able to determine whether execution of a phase has been completed, each phase can be separately scheduled and the results of preceding phases can be used to inform the scheduling of subsequent phases. In one example, different numbers of threads and/or different numbers of data instances per thread may be processed for different phases of the same program.

Multi-phased and multi-threaded program execution based on SIMD ratio

Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources assignable to the client inputs and tile inputs. The communications resources may include: multiple internal links, client outputs configured to interface with client circuits, and tile outputs configured to interface with one or more other tile instances. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results over multiple cycles.

Tiled processor communication fabric

A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data. At least one of the parameter decode unit, colour decode unit and weight decode unit are configured to decode intermediate data from the received block that is common to the decoding of at least a subset of texels of that block and to use that decoded intermediate data as part of the decoding of at least two of the plurality of texels from the received block of texture data.

Growing community of inventors

London, United Kingdom

Yoong Chert Foo