Samsung Electronics Co., Ltd.

Yoon-Jay Cho

Hyo-Jin Kim

Jae-il Byeon

Il-Hun Son

Jeong-seok Chae

Jeong-Seok Chae

Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.

Bidirectional high voltage switching device and energy recovery circuit having the same

A voltage reference generator includes a current source for generating a source current in response to a control voltage and a current sink for conducting the source current to generate a reference voltage. Additionally, a switch block is configurable to determine the level of the source current conducted through the current sink. Furthermore, a reference current generator includes transistors operating in weak inversion with an active load coupled to one of the transistors.

Voltage reference generator with flexible control of voltage

An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.

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Seoul, South Korea

Yoon-Jay Cho