Fairchild Korea Semiconductor Ltd.

Yoon-hwa Choi

Shi-baek Nam

Rajeev Dinkar Joshi

Maria Cristina B Estacio

O-seob Jeon

Sang-do Lee

A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip pad and encircled by a first insulating layer; a re-distributed line (RDL) pattern being formed on the same horizontal surface as the first insulating layer and the stud bump, the RDL pattern for connecting the stud bump and a solder bump; a second insulating layer for insulating the RDL pattern so that a portion of the RDL pattern that is connected with the solder bump is exposed; and the solder bump being attached to the exposed portion if the RDL pattern.

Wafer-level chip scale package having stud bump and method for fabricating the same

Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of a frame and a plurality of pillar-shaped portions supporting the top plates, a semiconductor chip attached onto edge portions of the leads, wires connecting the leads with corresponding bonding pad on the semiconductor chip, and a molding material encapsulating the semiconductor chip and the wires and parts of the leads so as to the bottom surfaces of the leads are exposed. Further, some embodiments have a conductive pad exhibiting higher heat dissipation.

Package frame and semiconductor package using the same

Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.

Molded leadless package having a partially exposed lead frame pad

A power semiconductor package is provided. The power semiconductor package includes a chip, leads, conductive media, and a molding material. The leads have a groove in the shape of a hemisphere or a down-set. The package further includes an adhesive. The package can increase solder joint reliability and thermal performance. Also, the size of the package can be reduced, and sawing can be performed so that a burr does not occur.

Growing community of inventors

Incheon, South Korea

Yoon-hwa Choi