Hitachi, Ltd.

Hitachi Microcomputer Eng. Ltd.

Hewlett-packard Company

Yooichi Shintani

Tohru Shonai

Eiki Kamada

Kazunori Kuriyama

Kiyoshi Inoue

Kenichi Wada

Akira Yamaoka

Shigeo Takeuchi

Tsuguo Shimizu

Shinji Fujiwara

Mitsuru Nagasaka

Rajiv Gupta

Naoki Hamanaka

Naohiko Irie

Toyohiko Kagimasa

Kanji Kubo

Yoshikazu Tanaka

William S Worley, Jr

Frederic C Amerson

B Ramakrishna Rau

Shizuo Gotou

Seiichi Yoshizumi

Mikiko Suzuki

An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

Information processing system and information processing method for

A sorting method used with a distributed database having a plurality of first processors for holding partial records of a database that is divided into a plurality of portions and a host processor for accessing to each of the first processors. The method comprises the steps of: assigning a plurality of sections into which the distribution range of key values of records of the database is partitioned to a plurality of second processors in the first processors, and information for representing storage positions of the records to the second processors to which the sections of the key values, to which the records belong, are assigned; and sorting the plurality of key values, which have been received, in the second processors to produce key tables in which the information for representing the storage positions of the records which has been received is registrated together with the sorted key values, as the sorting result.

Method for storing records of a distributed database by plural

To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Information processing apparatus with prefetch control for prefetching

A parallel database processing system a global database processing unit, a plurality of local database processing units, and a network interconnecting the global database processing unit and a plurality of local database processing units, wherein one table containing a number of records is partitioned into local tables, each local table being provided in a corresponding one of the local database processing units, secondary key indexes representing correspondence between the values of secondary keys for all records in the table and access information to the records corresponding to the secondary keys, are partitioned on the basis of the values into local secondary key indexes, each set of the local secondary key indexes being provided in a corresponding one of the local database processing units, and an identifying unit is provided in the global database processing unit, the identifying unit responsive to a retrieval request with the secondary key identifying the local database processing unit having the local secondary key index corresponding to the secondary key. At the global database processing unit, the retrieval request with the secondary key is received, the identifying unit identifies the local database processing unit having the local secondary key index corresponding to the secondary key, and the retrieval request with the secondary key is transferred to the identified local database processing unit. At the identified local database processing unit, its own local secondary key indexes are referred to obtain access information corresponding to the transferred retrieval request with the secondary key, and the retrieval request with the secondary key is processed by using the access information so that the local table corresponding to the retrieval request with the secondary key is accessed.

Parallel database processing system and retrieval method using secondary

An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.

Information processor providing enhanced handling of address-conflicting

Data processor for concurrent executing of instructions by plural

A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.

Data processor for parallelly executing conflicting instructions

A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.

Pipelined parallel data processing apparatus for directly transferring

A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.

Pipelined data processor capable of decoding and executing plural

An information processing apparatus for executing instructions in parallel includes circuitry which, when a first instruction requesting reading of an operand from a certain address of the main storage or buffer storage has been decoded, detects among instructions in execution the presence of a second instruction requesting writing of an operand held by a register such as a general-purpose register into that address of the main storage without implementing an operation on the operand. If the second instruction has been detected, the invention reads out an operand from the register specified for operand reading by said second instruction before operand writing into the main storage by the second instruction is completed.

Information processing apparatus for determining sequence of parallel

A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.

Data processor capable of executing instructions under prediction

A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

Data processing system

A data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The device includes a register control circuit for assigning one of a plurality of physical registers to store instructions when more than one of the instructions requires the use of the same logical register. This correspondence between the physical and logical registers is maintained while instructions are subsequently transferred to the arithmetic units where they are processed in parallel.

Data processing device

A mode register stores a mode bit for each of the general registers, an access circuit accesses the general registers and the mode register so that a general register designated by an instruction and a corresponding mode bit are read out together. A data use circuit or a data supply circuit connected to the general registers includes a circuit portion which effectively changes the significant bit length of the data read out of the designated general register or of the data to be written into the designated general register.

Growing community of inventors

Hadano, Japan

Yooichi Shintani