Samsung Electronics Co., Ltd.

Yoocheol Shin

Changhyun Lee

Hyunjung Kim

Byoungkeun Son

Chung-Il Hyun

Jungdal Choi

Jaesung Sim

Young-Ho Lee

Seok-Won Lee

Joonhee Lee

Hongsoo Kim

Dongseog Eun

Min Kyu Yang

Dongjun Seong

Jintaek Park

Jaegoo Lee

Young-Jin Kwon

Changyun Lee

Yongsik Yim

Hyunsu Ju

Jongsun Sel

Eunmi Kim

A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Semiconductor device including a stack having a sidewall with recessed and protruding portions

A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

Three-dimensional semiconductor memory device

A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

Semiconductor device and method of fabricating the same

Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby

Variable resistance memory devices and methods of forming the same are disclosed. The devices may include an additional barrier layer that is a portion of a variable resistance layer and that is formed before forming a horizontal electrode layer. Due to the presence of the additional barrier layer, it may be possible to cure loss or damage of the variable resistance layer.

Variable resistance memory device and methods of forming the same

A semiconductor device includes a substrate extending in a horizontal direction. An active pillar is present on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate. A variable resistive pattern is present on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof. A gate is present at a sidewall of the active pillar.

Three-dimensional resistive random access memory devices, methods of operating the same, and methods of fabricating the same

Resistive memory devices are provided having a gate stack including insulating layers and gates stacked on a substrate in a vertical direction, a channel penetrating the gate stack in the vertical direction to be electrically connected to the substrate, a gate insulating layer provided between the channel and the gates, and a variable resistance layer disposed along an extending direction of the channel. The gate stack may include an alcove formed by recessing the gate in a horizontal direction. The variable resistance layer may extend toward the alcove in the horizontal direction and be overlapped with at least one of the gates in the horizontal direction. Related methods are also provided.

Resistive random access memory devices having variable resistance layers and related methods

A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.

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Hwaseong-si, South Korea

Yoocheol Shin