Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Yoocharn Jeon

Martin Foltin

Erik Ordentlich

Hou Tee Ng

Gregg Bernard Lesartre

Naveen Muralimanohar

Scott T Haubrich

Richard H Henze

Hans S Cho

James Ignowski

Jianhua Yang

Gary A Gibson

Cyril Guyot

Brent Buchanan

Won Ho Choi

Alfred I-Tsung Pan

Alfred I Pan

Yongjune Kim

Yuval Cassuto

Richard Stanley Williams

Frederick A Perner

Christopher John Petti

Siamak Tavallaei

Tz-Yi Liu

Ali K Al-Shamma

Xia Sheng

David B Fujii

Jacquelyn M Ingemi

An apparatus is provided that includes a memory device including a plurality of sub-arrays, and a memory controller. The memory controller is configured to determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit, and write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.

Apparatus and methods for writing random access memories

Apparatuses and techniques are described for forming of selectors in a memory device such as a crosspoint memory array. A threshold switching selector is in series with a resistance-switching memory cell in a storage node. Prior to a first switching operation in the array, a stimulus is applied to the storage node to transform the selectors from an initial state having an initial threshold voltage to an operating state having a lower, operating threshold voltage. The stimulus can include a signal having a voltage which does not exceed the operating threshold voltage. To limit peak current consumption, the stimulus can be applied to different subsets of the array, one subset at a time.

Subthreshold voltage forming of selectors in a crosspoint memory array

Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

Magnetic random-access memory with selector voltage compensation

A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.

Write efficiency in magneto-resistive random access memories

A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

Reference column sensing for resistive memory

A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.

Data sensing in crosspoint memory structures

The resistance state of a memristor in a crossbar array is determined. For instance, a combined reference-sneak current is determined based on a reference voltage, a sense voltage, a non-access voltage, and a voltage applied to a target row line, and a combined read-sneak current is determined based on a read voltage, a sense voltage, a non-access voltage, and a voltage applied to a reference row line. The resistance state of a target memristor is then determined based on the combined reference-sneak current and the combined read-sneak current.

Determining resistance states of memristors in a crossbar array

In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.

Memristor memory with volatile and non-volatile states

A crossbar array with shared drivers has a plurality of sets of row lines, a set of row drivers, a plurality of sets of column lines, a set of column drivers, and a plurality of memory cells. Each set of row lines has a plurality of row lines and is driven by a set of row drivers. Furthermore, each set of row lines intersects with a plurality of the sets of column lines. Likewise, each set of column lines has a plurality of column lines and is driven by a set of column drivers. Each set of column lines intersects with a plurality of the sets of row lines. Each memory cell is coupled between an intersection of a row line and a column line.

Crossbar arrays with shared drivers

In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias voltage causes a bias current to pass through a target memristor along the target row line. The bias voltage is increased by a predetermined amount to a state voltage. A state current flowing through the target memristor is determined. The state current is based on the state voltage. A state of the target memristor is determined based on the state current.

Determining a state of memristors in a crossbar array

A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

Reusing sneak current in accessing memory cells

A multimodal memristor memory provides selectable or reconfigurable operation in a plurality of operational modes of a memristor. The multimodal memristor memory includes a memristor having a plurality of operational modes. The multimodal memristor memory further includes a reconfigurable interface driver to select an operational mode of the plurality of operational modes of the memristor. The memristor is to operate in the operational mode selected by the reconfigurable interface driver.

Multimodal memristor memory

This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

Sensing circuit for resistive memory

In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.

Sidewall spacers

Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.

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Palo Alto, CA, United States of America

Yoocharn Jeon