Samsung Electronics Co., Ltd.

Yoochang Sung

Changsik Yoo

Yonghun Kim

Jaemin Choi

Jeongdon Ihm

Jaewoo Jeong

Kyungryun Kim

Hundae Choi

Youngsoo Sohn

Seunghwan Hong

Jinhyeok Baek

Changhyun Bae

Younggil Go

An offset calibration training method for adjusting a data receiver offset and a memory device therefor are provided. A method of performing a data receiver offset calibration includes storing a first parameter code, which is used to set a default data receiver offset calibration for the data receiver offset calibration, in a mode register, storing a second parameter code, which is used to set an optional data receiver offset calibration for the data receiver offset calibration, in the mode register, training the default data receiver offset calibration based on the first parameter code for the data receiver offset calibration, and training the optional data receiver offset calibration based on the second parameter code for the data receiver offset calibration.

Offset calibration training method for adjusting data receiver offset and memory device therefor

A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same

A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.

Memory devices, memory systems having the same, and operating methods thereof

A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

Receiver for cancelling common mode offset and crosstalk

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

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Hwaseong-si, South Korea

Yoochang Sung