Samsung Electronics Co., Ltd.

Yoo-sang Hwang

Tae-Young Chung

Ki-nam Kim

Byung-Jun Park

Byung-jun Park

Se-myeong Jang

Jin-woo Lee

Hong-sik Jeong

Yoon-soo Chun

Hoon Jung

Mi-hyang Lee

An integrated circuit device includes a semiconductor substrate that has a cell region and a peripheral region that surrounds the cell region. A plurality of capacitors that include a plurality of lower electrodes, respectively, are disposed in the cell region. Supporters connect adjacent ones of the plurality of lower electrodes to provide structural support and stability to the lower electrodes.

Methods of forming integrated circuit devices including cylindrical capacitors having supporters between lower electrodes

A semiconductor device including storage nodes of a capacitor and a method for manufacturing the same are provided. Bit lines are formed on a semiconductor substrate, and protection layers are formed to cover and protect the bit lines. Conductive contact pads are formed between the bit lines and are level with the top surfaces of the protection layers. A node supporting layer is formed to cover the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. The mold layer, the etching stopper, and the node supporting layer are patterned, thereby forming opening holes exposing the conductive pads. Storage nodes are formed in the opening holes and have the shape of the profile of the opening holes. The mold layer exposed by the storage nodes is removed, thereby exposing the outer wall of each of the storage nodes positioned above the etching stopper.

Method for manufacturing a semiconductor device including storage nodes of capacitor

A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming a lightly doped impurity region between the gate stacks, forming a gate spacer along sidewalls of the gate stacks, forming a heavily doped impurity region to contact the lightly doped impurity region and to be aligned with the gate spacer, removing the gate spacer, forming an interlevel dielectric layer to fill a gap between the gate stacks, forming a groove on a gate conductive layer by etching an exposed top surface of the etch stopper and the gate sacrificial mask, forming a contact mask pattern for filling the groove, forming a contact hole to be self-aligned with respect to the contact mask pattern, and forming a contact pad in the contact hole.

Method of fabricating a DRAM semiconductor device

A storage element of a stacked capacitor having a high dielectric film for a semiconductor device and a method of fabricating the same, the storage element having a storage node comprising a bottom polysilicon layer, a barrier metal layer, and a transition metal layer with sidewall spacers formed on the barrier metal layer. The barrier metal layer and sidewall spacers prevent the polysilicon layer from being oxidized. The polysilicon layer is formed to a thickness that determines the height of the storage node. The transition metal layer directly interfacing the high dielectric film is thinly formed to avoid slope etching thereof and thereby prevent electrical bridges or shorts between adjacent storage nodes.

Capacitor of a semiconductor device and a method of fabricating the same

Methods of forming FRAM devices include the steps of forming first and second field effect access transistors in a semiconductor substrate, forming first and second bit lines (BL) electrically coupled to a drain region of the first field effect access transistor and a drain region of the second field effect access transistor, respectively, and forming first and second ferroelectric capacitors (C,) between the first and second bit lines in order to improve integration density. These first and second ferroelectric capacitors share a first electrode extending between the first and second bit lines and have respective second electrodes electrically coupled to respective source regions of the first and second field effect access transistors. The preferred methods may also include the step of forming a field oxide isolation region adjacent a face of the substrate and extending between the first and second field effect access transistors. In addition, a step may be provided to form a first interlayer dielectric layer on the first and second field effect access transistors and on the field oxide isolation region. The step of forming the first and second ferroelectric capacitors may also comprise the preferred steps of forming a first conductive layer on the first interlayer dielectric layer, forming a ferroelectric dielectric layer (e.g., PZT, PLZT) on the first conductive layer, forming a second conductive layer on the ferroelectric dielectric layer, patterning the second conductive layer and the ferroelectric dielectric layer using a first mask to define the second electrodes of the first and second ferroelectric capacitors and then patterning the first conductive layer using a second mask to define the first electrode which is shared by the first and second ferroelectric capacitors.

Growing community of inventors

Yongin, South Korea

Yoo-sang Hwang