Skhynix Inc.

Yoo Jong Lee

Kang Sub Kwak

Woongrae Kim

Tae Yong Lee

Sang Sic Yoon

Young Jun Yoon

A semiconductor device includes a power gating control block and a power gating circuit. The power gating control block activates a data power control signal during a period that is set by a target code, the period being from a point in time in which the semiconductor device enters a read mode or a write mode. In addition, the power gating control block deactivates an operation power control signal in a power-down mode. The power gating circuit inhibits a data power signal from being supplied to a data input/output block based on the data power control signal. Moreover, the power gating control block inhibits an operation power signal from being supplied to an internal operation control block based on the operation power control signal.

Semiconductor device with a power-down mode and a power gating circuit and semiconductor system including the same

A semiconductor device includes a phase control signal generation circuit, a phase detection circuit, and a selection/transmission circuit. The phase control signal generation circuit outputs one of a command-shifted signal generated from a command/address signal and a clock-shifted signal generated from a clock signal as a phase control signal, based on a leveling enablement signal. The phase detection circuit detects a phase of a leveling clock signal in synchronization with the phase control signal to generate a detection signal. The selection/transmission circuit outputs the detection signal as one of a phase detection signal and a phase adjustment signal based on the leveling enablement signal.

Semiconductor devices and semiconductor systems

A power gating circuit is provided. The power gating circuit includes a logic gate group. The power gating circuit also includes a first switching circuit coupled to first and second supply voltages and the logic gate group. The power gating circuit further includes a second switching circuit coupled to the first and second supply voltages and the logic gate group. The first and second supply voltages are supplied to the logic gate group through the first switching circuit based on a voltage select signal. The first and second supply voltages are supplied to the logic gate group through the second switching circuit based on the voltage select signal and a power down signal.

Power gating circuit and power gating control system

A semiconductor device includes a drive control circuit and a write control circuit. The drive control circuit generates a pre-drive control signal and a drive control signal based on a latch command and generates a pattern drive control signal based on a pattern latch command. The write control circuit stores drive data generated from data inputted based on the pre-drive control signal and the drive control signal or stores the drive data driven to a predetermined logic level based on the pattern drive control signal.

Semiconductor devices

A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.

Semiconductor systems

A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

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Suwon-si, South Korea

Yoo Jong Lee