Samsung Electronics Co., Ltd.

Yoo-Chul Kong

Kyoung-Sub Shin

Jong-Kyu Kim

Ji-Hoon Choi

Jin-Gyun Kim

Jae-Jin Shin

Yil-hyung Lee

Dae-Hyun Jang

Jin-Hyuk Yoo

Jung-ho Kim

Jung-Ho Kim

Sang-sup Jeong

Jong-chul Park

Seok-Woo Nam

Sang-Kuk Kim

Gyung-Jin Min

Doo-Young Lee

Suk-Ho Joo

Dae-hyun Jang

Seong-Soo Lee

Sang-Ryol Yang

Sang-ryol Yang

Hye-Ji Yoon

Jong-Soon Park

Han-Geun Yu

In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.

Method of processing a substrate using an ion beam and apparatus for performing the same

In a method of forming a pattern of a semiconductor device, a first mask layer and an anti-reflective coating layer may be sequentially formed on a substrate. A photoresist layer may be formed on the anti-reflective coating layer. The photoresist layer may be exposed and developed to form a first preliminary photoresist pattern. A first ion beam etching process may be performed on the first preliminary photoresist pattern to form a second preliminary photoresist pattern. A second ion beam etching process may be performed on the second preliminary photoresist pattern to form a photoresist pattern. A second incident angle of an ion beam in the second ion beam etching process may be greater than a first incident angle of an ion beam in the first ion beam etching process. The anti-reflective coating layer and the first mask layer may be etched using the photoresist pattern as an etching mask to form a mask structure.

Method of forming patterns and method of manufacturing a semiconductor device using the same

Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Semiconductor device

Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

Three dimensional semiconductor memory device and method of fabricating the same

A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Methods of manufacturing a semiconductor device and a semiconductor memory device thereby

A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.

Semiconductor device and method of manufacturing the same

Growing community of inventors

Seoul, South Korea

Yoo-Chul Kong